PMTS, PEX Engineer – Quantum

🕒 Ontem

🌐 Estados Unidos, Malta – Remoto

🇺🇸 Estados Unidos – Remoto (EUA) 🇲🇹 Malta – Remoto

🗽 New York, Massachusetts – Remoto

🗽 New York – Remote 🍂 Massachusetts – Remote

💵 $143.000 - $247.000 / ano

⏰ Tempo Integral

🟡 Pleno

🟠 Sênior

👷🏻‍♀️ Engenheiro

🦅 Patrocina Visto H1B

Esta empresa já patrocinou vistos H1B no passado.

👻 Score fantasma 2%

O que significa: a chance de ninguém estar realmente contratando para esta vaga.Como ler: 60% ou mais significa que achamos que é uma vaga fantasma. Pontuações mais baixas preocupam menos.Como pontuamos: tempo em aberto, republicações, vagas abertas vs tamanho do time, rapidez para fechar vagas, e se o salário está divulgado.Observação: é uma estimativa de dados públicos, não um julgamento da empresa. Vagas reais podem ter pontuação alta, então use como uma dica, não como um fato.

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GlobalFoundries

SiteLinkedInTodas as Vagas

10.000+ funcionários

🏭 Manufatura

🔧 Hardware

Manufacturing • Hardware

GlobalFoundries (GF) é um dos principais fabricantes de semicondutores do mundo. A GF está redefinindo a inovação e a fabricação de semicondutores ao desenvolver e entregar soluções de tecnologia de processo ricas em recursos que proporcionam desempenho de liderança em mercados de alto crescimento pervasivos. A GF oferece uma combinação única de serviços de design, desenvolvimento e fabricação. Com uma força de trabalho talentosa e diversificada e uma infraestrutura de manufatura em escala, que abrange os EUA, Europa e Ásia, a GF é uma fonte de tecnologia confiável para seus clientes em todo o mundo.

Descrição

• Develop, code, qualify, and maintain DRC, LVS, and PEX rule decks and associated PDK components • Translate process integration requirements, design rules, device definitions, and electrical models into physical verification and extraction solutions • Develop regression and test methodologies to validate rule-deck correctness, coverage, performance, scalability, and compatibility • Analyze and debug complex DRC, LVS, and PEX issues, identify root causes, and resolve discrepancies with cross-functional teams • Partner with process technology, design rule, compact modeling, reliability, circuit design, layout, and EDA teams • Develop automation and AI/ML-assisted methodologies for rule generation, test generation, coverage assessment, error classification, anomaly detection, debugging, and continuous PDK verification • Optimize physical verification and extraction flows for accuracy, runtime, memory usage, scalability, usability, and production deployment • Drive PDK quality and release readiness through qualification, regression testing, documentation, change management, and continuous improvement • Perform activities safely and support Environmental, Health, Safety & Security programs • Work and collaborate on other projects and assignments as needed

🎯 Requisitos

• Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field • Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level • Experience with DRC and/or LVS rule development, coding, debug, or qualification • Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance • Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions • Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies • Experience with Python, Tcl, Perl, shell scripting, or equivalent for engineering automation, regression testing, and data analysis • Ability to troubleshoot complex technical problems, perform structured root-cause analysis, and translate findings into robust engineering solutions • Willingness to travel up to 10% • Written and verbal fluency in English • Preferred: Master's degree or PhD in a related technical field • Preferred: Experience releasing production PDK DRC, LVS, and/or PEX rule decks • Preferred: Experience with Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or equivalent • Preferred: Experience with PEX technology-file development, RC extraction, process-corner modeling, and silicon/model correlation • Preferred: Experience with automated regression environments, rule coverage metrics, test structures, or PDK qualification methodologies • Preferred: Experience applying AI/ML, generative AI, or data-driven techniques to semiconductor design enablement • Preferred: Understanding of interactions among process integration, design rules, OPC/lithography, device modeling, reliability, extraction, and circuit design • Preferred: Experience collaborating with EDA vendors and design teams • Preferred: Strong written and verbal communication skills • Preferred: Strong planning and organizational skills

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