Senior DFT Engineer

🕒 Junho 24

🇺🇸 Estados Unidos – Remoto (EUA)

💵 $170.000 - $250.000 / ano

⏰ Tempo Integral

🟠 Sênior

👷🏻‍♀️ Engenheiro

👻 Score fantasma 23%

O que significa: quão provável esta vaga está aberta sem contratação ativa.Como ler: 60% ou mais significa que achamos que é uma vaga fantasma. Pontuações mais baixas preocupam menos.Como pontuamos: tempo em aberto, republicações, vagas abertas vs tamanho do time, rapidez para fechar vagas, e se o salário está divulgado.Observação: é uma estimativa de dados públicos, não um julgamento da empresa. Vagas reais podem ter pontuação alta, então use como uma dica, não como um fato.

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K2 Space Corporation

SiteLinkedInTodas as Vagas

11 - 50 funcionários

Fundada em 2022

🎖️ Defesa

📦 Logística

🏭 Manufatura

Defense • Logistics • Manufacturing

Tornando possíveis missões anteriormente impossíveis

Descrição

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation. • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. • Contribute to methodology development, automation, and flow improvements.

🎯 Requisitos

• B.S. or M.S. in Electrical Engineering or related field. • 7+ years of experience in DFT for complex SoCs. • Strong hands-on experience with RTL DFT insertion (scan, compression, test points) and ATPG tools and flows. • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. • Experience with low-power DFT techniques. • Familiarity with mixed-signal integration challenges and test methodologies. • Strong debugging skills across RTL, gate-level, and silicon.

🏖️ Benefícios

• Comprehensive benefits package including paid time off • Medical/dental/vision coverage • Life insurance • Paid parental leave • Many other perks