Senior Power Integrity Engineer

🕒 il y a 4 jours

🇬🇧 Royaume-Uni – Télétravail

⏰ Temps Plein

🟠 Senior

👷🏻‍♀️ Ingénieur

👻 Score fantôme 12%

Ce que ça veut dire : la probabilité que cette offre reste ouverte sans recrutement actif.Comment le lire : 60 % ou plus, on pense que c'est une offre fantôme. Un score plus bas est moins inquiétant.Comment on la calcule : ancienneté, republications, postes ouverts vs taille de l'équipe, rapidité de clôture, et si le salaire est indiqué.À noter : une estimation à partir de données publiques, pas un jugement sur l'entreprise. De vraies offres peuvent avoir un score élevé, alors prenez-le comme un indice, pas comme un fait.

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DriveNets

Site WebLinkedInTous les Emplois

201 - 500 employés

📡 Télécommunications

Telecommunications

DriveNets est une entreprise de logiciels en pleine croissance qui a développé une nouvelle approche radicale permettant aux fournisseurs de services et hyperscalers de construire leur infrastructure réseau. DriveNets Network Cloud et DriveNets Network Cloud-AI sont de nouvelles solutions innovantes de mise en réseau qui appliquent l'architecture cloud à des réseaux de grande envergure. Elles allient la scalabilité de l'architecture standard Ethernet Clos à la haute performance et à la fiabilité du réseau fournisseur de services, offrant ainsi une performance réseau optimale, une grande échelle et une structure de coûts appropriée pour les fournisseurs de services et hyperscalers.

Description

• Lead Power Integrity activities throughout the hardware development lifecycle, from architecture through production • Define and optimize board-level and package-level Power Delivery Networks for high-current networking ASICs and supporting devices • Perform pre-layout and post-layout PI simulations using industry-standard tools • Establish target impedance requirements and validate compliance across all power rails • Analyze DC voltage drop, AC impedance, transient response, and power distribution performance • Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing • Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces • Develop power integrity design guidelines and best practices for next-generation networking products • Support schematic reviews, layout reviews, and design sign-off activities • Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment • Investigate and resolve PI-related issues during board bring-up, validation, and production • Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance • Drive continuous improvement of PI methodologies, simulation flows, and validation processes • Achieve PI sign-off requirements for all networking platforms • Minimize power-related issues during bring-up and production • Improve first-pass hardware success rate • Enable reliable operation of next-generation high-bandwidth networking systems • Establish scalable PI methodologies for future DriveNets hardware platforms

🎯 Exigences

• B.Sc. or M.Sc. in Electrical Engineering • 5+ years of experience in Power Integrity, Hardware Design, or related disciplines • Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts • Hands-on experience with PI simulation tools such as Cadence Sigrity PowerSI / OptimizePI, Ansys SIwave, Ansys HFSS, and PowerDC or equivalent • Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products • Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity • Experience with multi-phase voltage regulators, power sequencing, and power management architectures • Strong understanding of PCB materials, stackups, and manufacturing constraints • Experience performing lab validation and correlation measurements • Experience with oscilloscopes, VNAs, power analyzers, current probes, and related laboratory equipment • Preferred: Experience with high-performance networking ASICs and switch silicon • Preferred: Familiarity with 112G/224G/448G PAM4 SerDes technologies • Preferred: Experience with Ethernet systems ranging from 400G to 1.6T and above • Preferred: Understanding of package-level PI and advanced packaging technologies • Preferred: Familiarity with optical networking platforms and co-packaged optics • Preferred: Experience with thermal and mechanical effects on PDN performance • Preferred: Knowledge of EMI/EMC considerations in high-density networking systems • Preferred: Experience working with ODMs, CMs, and global manufacturing partners

🏖️ Avantages

• Work on industry-leading networking systems deployed by top-tier service providers and cloud operators • Influence next-generation networking hardware architecture • Collaborate with world-class hardware, ASIC, and software engineers • Be part of a fast-growing company transforming the networking industry