ASIC Physical Design Lead

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🕒 August 5

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Niobium Microsystems

WebsiteLinkedInAll Job Openings

11 - 50 employees

🏭 Manufacturing

💼 Consulting

🏥 Healthcare

💰 $90k Grant on 2021-11

Manufacturing • Consulting • Healthcare

Niobium Microsystems is a company revolutionizing the field of data privacy and zero trust computing by offering FHE (Fully Homomorphic Encryption) solutions. They have developed the industry's first purpose-built FHE hardware accelerator, a PCIe card that significantly enhances the performance of FHE software across all major schemes, supporting seamless integration into various applications such as cloud computing, fraud detection, and medical research. Their technology guarantees the privacy of data even during processing, ensuring that sensitive information remains secure. Niobium partners with leading organizations to bring guaranteed privacy to generative AI applications and pushes for standards in quantum-resilient cryptography.

📋 Description

• Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery • Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow • Architect and execute floorplanning strategies for large, hierarchical SoCs • Integrate IPs and macros, define physical partitions and hierarchy, and establish power grid and clock distribution topology • Collaborate with Architecture and RTL teams on physical feasibility, timing closure readiness, and area/power targets • Lead block-level and top-level place and route using industry-standard EDA tools • Drive timing convergence across corners, modes, voltage domains, and operating conditions • Own PPA optimization, congestion mitigation, and physical integrity • Implement CTS and optimize skew, latency, and clock power • Lead IR/EM sign-off strategy, thermal analysis, and full-chip physical verification • Integrate and validate low-power methodologies, including UPF/CPF flows • Partner with DFT and PD teams on scan insertion, BIST structures, test modes, and timing • Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing • Set physical design quality standards, conduct design reviews, and ensure execution through tapeout • Provide technical leadership, mentorship, and coaching to junior and mid-level physical designers • Champion continuous improvement across flows, scripts, and design methodology

🎯 Requirements

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field; advanced degree preferred for leadership roles • 8+ years of relevant experience in ASIC Physical Design • Strong track record of multiple tape-outs at advanced technology nodes; 16nm → 3nm preferred • Deep expertise in floorplanning • Deep expertise in place and route • Deep expertise in CTS • Deep expertise in STA/timing closure • Deep expertise in physical verification and sign-off • Deep expertise in low-power design and UPF • Strong hands-on proficiency with Cadence and/or Synopsys physical design toolchains • Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities • Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans • Strong communication skills for articulating technical decisions across cross-functional teams • Ability to operate effectively in a distributed team environment • Ability to own schedules, deliverables, and quality in a fast-moving development cycle • Exceptional analytical, debugging, and problem-solving skills with meticulous attention to detail

🏖️ Benefits

• Competitive salaries • Equity in the form of Incentive Stock Options (ISO) • Employer paid medical insurance plan • Health Savings Account (HSA) with employer contributions • Dental and vision reimbursement account (HRA) • 401(k) retirement plan with employer match • Flexible work location with remote options • Flexible time off