Senior ASIC Emulation Engineer

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K2 Space Corporation

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11 - 50 employés

Fondée en 2022

🎖️ Défense

📦 Logistique

🏭 Fabrication

Defense • Logistics • Manufacturing

K2 Space Corporation est un fabricant aérospatial basé en Californie qui conçoit et produit de grands bus satellites à haute puissance destinés à offrir significativement plus de puissance, de masse et de volume de charge utile à moindre coût que les grands satellites traditionnels. L'entreprise met l'accent sur des constructions de type chaîne de production et des chaînes d'approvisionnement commerciales pour raccourcir les délais de livraison et réduire le coût unitaire, permettant ainsi des lancements multi-manifestations et des missions multi-orbitales à travers les espaces LEO, MEO, GEO et cislunaire. K2 sert des clients commerciaux, scientifiques et gouvernementaux/défense, et se concentre sur la facilitation des missions nécessitant des charges utiles à haut débit et à haute puissance.

Description

• Lead the bring-up, deployment, and optimization of pre-silicon emulation platforms. • Build, integrate, and maintain full-chip, multi-chip, and system-level emulation models on Palladium, ZeBu, or Veloce. • Define and evolve emulation strategy, methodology, and workflows across the ASIC organization. • Compile, map, and optimize RTL designs for emulation performance, capacity, and stability. • Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces. • Support system-level hardware/software integration, complex use-case validation, and representative end-to-end workloads. • Help the DV team run targeted, high-value emulation tests and optimize flows to reduce simulation bottlenecks. • Enable firmware, bootloader, driver, and software teams with emulation platforms and HW/SW integration debugging. • Run emulation workloads, triage failures, perform root-cause analysis, and resolve issues with design and verification teams. • Maintain and enhance automation for compile flows, regression management, and continuous integration. • Participate in architecture reviews and microarchitecture discussions and influence design-for-emulation practices. • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation. • Manage interactions with external IP providers or emulation partners when needed. • Collaborate with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams.

🎯 Exigences

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field. • 5+ years of experience in ASIC/SoC development focused on emulation. • Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles. • Hands-on expertise with Palladium, ZeBu, or Veloce, including model build, debugging, and performance optimization. • Proficiency with Python, Perl, and TCL for automation and tooling. • Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing. • Familiarity with APB, AHB, AXI, JTAG, and SPI buses and protocols. • Experience driving cross-functional debugging involving RTL, DV, firmware, physical design, and validation teams. • Understanding of pre- and post-silicon debugging methodologies and correlation workflows. • Must be a U.S. Person as defined by ITAR or otherwise eligible for a federally issued export-control license. • Nice to have: experience with FPGA prototyping platforms, low-power modes and power-aware emulation, analog/mixed-signal behavioral models, SERDES, PCIe, Ethernet, USB, or multi-gigabit PHYs.

🏖️ Avantages

• Equity in the company • Comprehensive benefits package • Paid time off • Medical coverage • Dental coverage • Vision coverage • Life insurance • Paid parental leave • Other perks • Reasonable accommodation during employment application or interviews