Senior DFT Engineer

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K2 Space Corporation

Site WebLinkedInTous les Emplois

11 - 50 employés

Fondée en 2022

🚀 Aérospatiale

🔧 Matériel

🏛️ Gouvernement

Aerospace • Hardware • Government

K2 Space Corporation est un fabricant aérospatial basé en Californie qui conçoit et produit de grands bus satellites à haute puissance destinés à offrir significativement plus de puissance, de masse et de volume de charge utile à moindre coût que les grands satellites traditionnels. L'entreprise met l'accent sur des constructions de type chaîne de production et des chaînes d'approvisionnement commerciales pour raccourcir les délais de livraison et réduire le coût unitaire, permettant ainsi des lancements multi-manifestations et des missions multi-orbitales à travers les espaces LEO, MEO, GEO et cislunaire. K2 sert des clients commerciaux, scientifiques et gouvernementaux/défense, et se concentre sur la facilitation des missions nécessitant des charges utiles à haut débit et à haute puissance.

Description

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation. • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. • Contribute to methodology development, automation, and flow improvements.

🎯 Exigences

• B.S. or M.S. in Electrical Engineering or related field. • 7+ years of experience in DFT for complex SoCs. • Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. • Experience with low-power DFT techniques. • Familiarity with mixed-signal integration challenges and test methodologies. • Strong debugging skills across RTL, gate-level, and silicon.

🏖️ Avantages

• Base salary range for this role is $170,000 – $250,000 + equity in the company • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks