Senior Signal Integrity Engineer

🔥 16 hours ago

🇬🇧 United Kingdom – Remote

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 10%

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DriveNets

WebsiteLinkedInAll Job Openings

201 - 500 employees

📡 Telecommunications

Telecommunications

DriveNets is a rapidly growing software company that has created a radical new way for service providers and hyperscalers to build their networking infrastructure. DriveNets Network Cloud and DriveNets Network Cloud-AI are innovative networking solutions that apply the cloud architectural approach to high-scale networking, combining the scalability of standard Ethernet Clos architecture with the high performance and reliability of service provider networking. Founded by successful telco entrepreneurs Ido Susan and Hillel Kobrinsky, DriveNets offers the leading open disaggregated networking solution utilizing cloud-native software on standard white boxes. Their solutions are globally adopted by numerous service providers and are in various trials, significantly impacting network operations, including a substantial deployment with AT&T.

📋 Description

• Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces • Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths • Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues • Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices • Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis • Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs • Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process • Develop behavioural models based on measured signal integrity data to inform future design and simulation work • Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces

🎯 Requirements

• Bachelor's or Master’s degree in Electrical/Electronics Engineering with 10+ years of relevant experience • Strong understanding of electromagnetic (EM) concepts and transmission line theory • Extensive experience in signal integrity analysis for high-speed serial interfaces, including Ethernet, PCIe, and DDR5 • Proficiency in using EDA tools like Ansys SIWAVE, HFSS, or similar • Hands-on expertise in time-domain and frequency-domain analysis, jitter, loss, and eye-diagram analysis • Strong background in HSPICE simulations and model development • Experience with PCB layout techniques for high-speed designs • Excellent communication skills and the ability to work effectively in a collaborative team environment • Experience with advanced simulation tools and techniques • Experience with high-speed interfaces such as 112Gbps PAM4 Ethernet, PCIe Gen5, and DDR5 • In-depth knowledge of high-speed PCB design and layout principles • Familiarity with power integrity and power noise simulations