Senior ASIC Design Verification Engineer

🔥 43 minutos atrás

🇺🇸 Estados Unidos – Remoto (EUA)

💵 $170.000 - $250.000 / ano

⏰ Tempo Integral

🟠 Sênior

✍️ Designer

👻 Score fantasma 21%

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Descrição

• Verify the functionality, performance, and robustness of custom silicon designs. • Define the verification approach and contribute to verification methodology. • Develop and execute block-level, subsystem-level, and full-chip verification plans. • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. • Write SystemVerilog Assertions and integrate formal verification where appropriate. • Drive constrained-random and directed testing strategies for functionality, corner cases, and stress scenarios. • Run simulations, triage failures, perform root-cause analysis, and collaborate with RTL designers to resolve issues. • Implement and maintain functional, code, and assertion coverage and ensure coverage closure for sign-off. • Manage regression testing, simulation farms, and CI pipelines. • Participate in design reviews, microarchitecture discussions, and design-for-verification best practices. • Collaborate with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. • Participate in ASIC team interviews. • Advance design verification methodologies and improvements. • Engage external IP providers and verification partners when needed.

🎯 Requisitos

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. • 5+ years of experience in ASIC/SoC verification. • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows. • Proficiency with a simulation tool such as VCS, Xcelium, or Questa. • Proficiency with waveform debug tools such as Verdi or SimVision. • Proficiency with a coverage tool. • Proficiency with scripting languages such as Python, Perl, or TCL. • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation. • Understanding of industry-standard interfaces such as APB, AHB, or AXI. • Familiarity with embedded processor-based designs and firmware/bare metal coding such as C or C++. • Must be a “U.S. person” as defined by ITAR or otherwise eligible for a federally issued export control license. • Nice-to-have: Experience with developing and integrating reference models. • Nice-to-have: Understanding of low power verification. • Nice-to-have: Familiarity with gate-level simulation and analog behavioral models. • Nice-to-have: Involvement in post-silicon validation planning and execution. • Nice-to-have: Experience working in cross-functional, geographically distributed teams. • Experience in space, telecom, or RF/digital mixed systems is a plus.

🏖️ Benefícios

• Equity in the company • Paid time off • Medical coverage • Dental coverage • Vision coverage • Life insurance • Paid parental leave • Many other perks • Reasonable accommodation for employment applications or interviews

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