Staff SoC Verification Engineer

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November 25

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Innatera

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Artificial Intelligence • Hardware • B2B

Innatera is a Netherlands-based developer of ultra-low-power neuromorphic processors and supporting software, including the Spiking Neural Processor (Pulsar T1) and the Talamo SDK. The company builds analog-mixed-signal chips that run spiking neural networks (SNNs) to deliver always-on, low-latency pattern recognition and sensor processing for power-constrained and latency-critical edge applications. Innatera targets sensor, IoT and embedded-system customers who need brain-inspired, event-driven cognition close to the sensor.

51 - 200 employees

🤖 Artificial Intelligence

🔧 Hardware

🤝 B2B

📋 Description

• Develop and maintain SystemVerilog/UVM-based verification environments at both module and SoC level; • Write test sequences, define functional coverage models, and ensure coverage closure; • Debug simulation results using waveform tools and collaborate with design teams to resolve issues; • Drive constrained-random stimulus generation and continuous improvements in our verification methodology; • Apply modern EDA tools and automate verification flows to maximize speed and quality; • Contribute to quality assurance, release-readiness, and design-test alignment for every chip.

🎯 Requirements

• 8+ years of digital verification, including 4+ years of constrained-random verification with UVM. • 2+ years of embedded C development for SoC verification. • Experience designing verification architecture from design specifications and creating test plans. • Ability to translate functional requirements into functional coverage models. • Skilled in constrained-random stimulus generation and coverage analysis/closure. • Strong expertise in root-cause analysis and debugging SystemVerilog RTL. • Proficiency in scripting with Python or similar languages. • Solid experience with Linux, bash, or equivalent environments. • Proficient with commercial EDA tools. • Experience collaborating effectively with cross-functional teams. • Hands-on experience with UVM verification architecture and vertical reuse of lower-level UVCs/environments. • Skilled in mixed-language simulation and system modeling. • Experience with effort estimation, project planning, scheduling, and tracking. • Proven ability to lead and mentor a small team.

🏖️ Benefits

• Competitive salary. • Pension plan. • A flexible working environment (work-from-home policy, flexible working hours, advantageous holidays scheme). • A generous holiday scheme. • A collaborative, ambitious team with the freedom to innovate. • An inclusive culture that values openness, curiosity, and personal growth. • Office perks like fresh fruit, snacks, and an on-site gym. • Statutory commuting/home allowance.