FPGA Circuit Design Engineer

Job not on LinkedIn

January 31

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Logo of Intel Corporation

Intel Corporation

Hardware • Artificial Intelligence • Telecommunications

Intel Corporation is a leading technology company that specializes in manufacturing and selling a variety of hardware and software products. Its offerings include processors such as Intel Core, Intel Xeon, and Intel Atom, as well as discrete graphics, AI accelerators, silicon photonics, and embedded solutions. Intel serves various industries with its networking, storage solutions, and developer resources, focusing heavily on AI and performance-driven technologies. The company plays a significant role in advancing computing experiences across PCs, data centers, cloud, edge, and 5G networks. Intel is committed to delivering high performance and secure technologies while fostering innovation through its expansive partner ecosystem and development tools.

10,000+ employees

Founded 1968

đź”§ Hardware

🤖 Artificial Intelligence

📡 Telecommunications

đź“‹ Description

• Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip. • Micro-architects and performs circuit and logic design, schematic entry, simulation, reliability verification, and verifies functionality to optimize FPGA circuits for power, performance, area, timing, and yield goals. • Develops models and collaterals for FPGA circuits and IPs to integrate into FPGA hardware and software deliverables including circuit integration specifications, behavioral models, electrical rule checkers, design intent, and timing and power models. • Collaboration with teams in different time zones to deliver best in class product.

🎯 Requirements

• Bachelor’s degree in electrical/Electronic Engineering or Computer Engineering is required. • More than 5 years of experience in CMOS circuit design is preferred. • Capable of reviewing the design within a broader team. • Understand physics behind latest CMOS design process and layout dependent impact on performance, power and area.

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