Digital Flow Enablement Solutions Architect

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🕒 il y a 2 mois

🏄 California, Massachusetts – Distant

🏄 California – Remote 🍂 Massachusetts – Remote

💵 $157 500 - $292 500 / an

⏰ Temps Plein

🟠 Senior

🔴 Expert

💻 Ingénieur Solutions

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Cadence Design Systems

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10 000+ employés

Cadence est un leader incontournable dans la conception électronique et de systèmes, s'appuyant sur plus de 30 ans d'expertise en logiciels de calcul. L'entreprise applique sa stratégie sous-jacente de Conception Intelligente de Systèmes pour fournir des logiciels, du matériel et de la propriété intellectuelle qui transforment les concepts de design en réalité. Les clients de Cadence sont parmi les entreprises les plus innovantes au monde, proposant des produits électroniques extraordinaires allant des puces aux cartes, jusqu'aux systèmes complets pour les applications de marché les plus dynamiques, y compris le calcul à grande échelle, les communications 5G, l'automobile, la téléphonie mobile, l'aérospatial, la consommation, l'industrie et la santé. Depuis huit années consécutives, le magazine Fortune a classé Cadence parmi les 100 meilleures entreprises où travailler.

Description

• Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development. • Interfacing with customers regarding digital flow enablement and methodologies, including: timing characterization, including sensitivity modeling, Physical view generation (LEF, GDS, abstracts, etc) Logical view generation (LIB, CDL, Spectre, etc) Technology LEF creation for digital tools MSOA flows • Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness • Tempus timing flow development and validation • Working closely with R&D on tools and methodology improvements • Other digital P&R tasks as needed by the group • Processes nodes range from 1.4nm to 350nm, with majority of work at GAA advanced nodes

🎯 Exigences

• Bachelor’s degree with at least 12-16 years of design/EDA experience or Master’s degree with at least 10 years of experience. • Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects • Excellent digital simulation and debug skills • Experience with techLEF development at advanced nodes a must • Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM • Strong knowledge of Digital Design flows and Static Timing Analysis • Prior experience with ASIC digital implementation flows and EDA tools is required • Experience with advanced nodes (5nm and below) required. • Good programming knowledge in Unix, Shell scripting, perl and importantly TCL • Strong customer-facing communication and problem solving skills • Strong personal drive for continuous learning and expanding professional skill sets • Excellent verbal and written communication skills • Familiar with EDA tool: Characterization: Liberate, Liberate MX, Liberate AMS Simulators: Spectre, AMS, Xcelium Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc

🏖️ Avantages

• paid vacation and paid holidays • 401(k) plan with employer match • employee stock purchase plan • a variety of medical, dental and vision plan options • and more.