Principal DFT Engineer

🕒 March 19

🇺🇸 United States – Remote

💵 $180k - $220k / year

⏰ Full Time

🔴 Lead

👷🏻‍♀️ Engineer

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EnCharge AI

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🤖 Artificial Intelligence

🔧 Hardware

🤝 B2B

💰 $100M Series B - EnCharge AI on 2025-02

Artificial Intelligence • Hardware • B2B

EnCharge AI is a company that develops analog in-memory computing hardware and complementary software to accelerate on-device and edge-to-cloud AI workloads. Their technology includes the EN100 analog AI accelerator and other form factors (chiplets, ASICs, PCIe cards) designed to deliver much higher energy efficiency, compute density, and lower total cost of ownership for inference compared with conventional GPUs and digital accelerators. EnCharge emphasizes sustainability, data privacy through local processing, and deployment for enterprise and developer customers seeking efficient, scalable AI computation outside traditional cloud infrastructure.

📋 Description

• Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. • Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. • Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST. • Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis. • Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

🎯 Requirements

• 10+ years in DFT, with at least 2 years in a leadership or principal role. • Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Genus/Modus). • Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6). • Proven track record with FinFET nodes (7nm, 5nm, or below). • Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.