Staff Physical Design Engineer

🕒 September 8

🌐 United States, Canada – Remote

🇺🇸 United States – Remote 🇨🇦 Canada – Remote

💵 $170k - $240k / year

⏰ Full Time

🔴 Lead

🧑‍🔧 Mechanical Engineer

🦅 H1B Visa Sponsor

This company has sponsored H1B visas in the past.

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EnCharge AI

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🤖 Artificial Intelligence

🔧 Hardware

🤝 B2B

💰 $100M Series B - EnCharge AI on 2025-02

Artificial Intelligence • Hardware • B2B

EnCharge AI is a company that develops analog in-memory computing hardware and complementary software to accelerate on-device and edge-to-cloud AI workloads. Their technology includes the EN100 analog AI accelerator and other form factors (chiplets, ASICs, PCIe cards) designed to deliver much higher energy efficiency, compute density, and lower total cost of ownership for inference compared with conventional GPUs and digital accelerators. EnCharge emphasizes sustainability, data privacy through local processing, and deployment for enterprise and developer customers seeking efficient, scalable AI computation outside traditional cloud infrastructure.

📋 Description

• Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing. • Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques. • Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution. • Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies. • Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution. • Translate complex microarchitectures into high-performance, power-efficient silicon. • Own implementation from netlist to successful foundry tapeout.

🎯 Requirements

• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. • 10–15 years of dedicated experience in physical design. • Strong understanding of EDA implementation flows with extensive experience using Cadence design tools. • Deep understanding of static timing analysis (STA) concepts and advanced timing closure methodologies. • Demonstrated success in top-level and block-level physical design, with hierarchical floorplanning expertise a strong plus. • Proficiency in low-power design techniques, debugging, and EM/IR check resolution/power grid verification. • Strong scripting skills in Tcl or Python for design flow automation. • Solid understanding of advanced process nodes and physical verification requirements associated with routing. • Experience with physical design methodology, flow setup, and advanced flow evaluations. • Prior experience with PDK management or foundry tapeout processes is highly desirable. • Equal employment opportunity employer in the United States.