Principal ASIC Design Verification Engineer

🕒 June 26

🇺🇸 United States – Remote

💵 $190k - $285k / year

⏰ Full Time

🔴 Lead

✍️ Designer

👻 Ghost score 27%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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K2 Space Corporation

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🎖️ Defense

📦 Logistics

🏭 Manufacturing

Defense • Logistics • Manufacturing

K2 Space Corporation is a California-based aerospace manufacturer that designs and produces large, high-power satellite buses intended to deliver significantly more power, mass and payload volume at lower cost than traditional large satellites. The company emphasizes production-line style builds and commercial supply chains to shorten lead times and reduce per-unit cost, enabling multi-manifest launches and multi-orbit missions across LEO, MEO, GEO and cislunar space. K2 serves commercial, scientific and government/defense customers, and focuses on enabling missions that require high throughput, high-power payloads.

📋 Description

• Verify the functionality, performance, and robustness of custom silicon designs. • Define verification approach and contribute to methodology. • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off. • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices. • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. • Participate in ASIC team interviews. • Drive advancement of DV methodologies and improvements. • Manage external IP providers and verification partners when needed. • Take lead on large and/or complex systems.

🎯 Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. • 10+ years of experience in ASIC/SoC verification. • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows. • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL). • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation. • Experience with developing and integrating reference models. • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI). • Involvement in post-silicon validation planning and execution.

🏖️ Benefits

• Comprehensive benefits package including paid time off • Medical/dental/vision coverage • Life insurance • Paid parental leave • Other perks