Senior DFT Engineer

🕒 June 24

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K2 Space Corporation

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🎖️ Defense

📦 Logistics

🏭 Manufacturing

Defense • Logistics • Manufacturing

K2 Space Corporation is a California-based aerospace manufacturer that designs and produces large, high-power satellite buses intended to deliver significantly more power, mass and payload volume at lower cost than traditional large satellites. The company emphasizes production-line style builds and commercial supply chains to shorten lead times and reduce per-unit cost, enabling multi-manifest launches and multi-orbit missions across LEO, MEO, GEO and cislunar space. K2 serves commercial, scientific and government/defense customers, and focuses on enabling missions that require high throughput, high-power payloads.

📋 Description

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation. • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. • Contribute to methodology development, automation, and flow improvements.

🎯 Requirements

• B.S. or M.S. in Electrical Engineering or related field. • 7+ years of experience in DFT for complex SoCs. • Strong hands-on experience with RTL DFT insertion (scan, compression, test points) and ATPG tools and flows. • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. • Experience with low-power DFT techniques. • Familiarity with mixed-signal integration challenges and test methodologies. • Strong debugging skills across RTL, gate-level, and silicon.

🏖️ Benefits

• Comprehensive benefits package including paid time off • Medical/dental/vision coverage • Life insurance • Paid parental leave • Many other perks