Physical Design Engineer

🕒 June 27

🇺🇦 Ukraine – Remote

⏰ Full Time

🟡 Mid-level

🟠 Senior

🧑‍🔧 Mechanical Engineer

👻 Ghost score 34%

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Capgemini

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1967

💼 Consulting

🏥 Healthcare

📦 Logistics

Consulting • Healthcare • Logistics

Capgemini is a global leader in partnering with businesses to transform and manage their operations by harnessing the power of technology. With expertise across a wide array of industries such as aerospace, automotive, banking, and healthcare, Capgemini provides a constantly evolving portfolio of services to meet the ever-changing needs of their clients. Their offerings include cloud, cybersecurity, data and artificial intelligence, and enterprise management, among others. Capgemini also emphasizes innovation and sustainability, helping companies achieve digital transformation while promoting environmental and social responsibility. Additionally, Capgemini provides career opportunities across various levels and professions, encouraging innovation and diversity in its workforce.

📋 Description

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below) • In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route • Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing) • In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes • Be part of the overall Low Power solution development and implementation • Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level) • Complete multiple design cycles of high complexity with little supervision

🎯 Requirements

• 5+ years in challenging RTL2GDSII work on 10nm or below nodes with 500k – 1million+ instances in designs • Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence • Good knowledge of synthesis flow, insertDFT scan/coverage and optimization • Excellent floorplan, power plan, CTS, place, route, and timing closure skills • Proficiency using Perl/TCL/Python scripting and Makefile • Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill • Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills • Experience with sign-off tape-out closure work

🏖️ Benefits

• Health insurance from the first days, regardless of the probationary period • Christmas holidays from December 25 to December 31 • Cooperation with Superhumans center and Veteran HUB • Psychological rehabilitation department of Superhumans • Psychological counseling provided by the Veteran Hub • Internal policy making the company friendly to military and veterans

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