ASIC Engineering Technical Lead – DFT

🔥 31 minutes ago

🍁 Vermont – Remote

🍁 Vermont – Remote

💵 $149.1k - $218.9k / year

⏰ Full Time

🟠 Senior

🔧 Hardware Engineer

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Cisco

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1984

🔧 Hardware

🔐 Security

🏢 Enterprise

Hardware • Security • Enterprise

Cisco is a multinational technology company that provides networking hardware, software, and services to enterprises, service providers, and governments. It builds routers, switches, optical transceivers, programmable silicon, and edge computing platforms, and offers security, collaboration (Webex), observability, and AI-enabled software and support services to help organizations design, operate, and secure large-scale networks and data centers. Cisco also delivers professional services, training, and cloud-managed solutions to support digital transformation and AI-ready infrastructure.

📋 Description

• leading development of DFT solutions for next-generation ASICs • Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST • Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models • drive scan-based diagnosis methodology for Silicon failure debug • provide post-silicon testing and validation support • evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems • Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations • Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

🎯 Requirements

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience • Prior experience working with ASICs • Prior experience in scan insertion and DFT setup, integration and validation • Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST. • 10+ years of experience working with ASICs (preferred) • 10+ years of experience in scan insertion and DFT setup, integration and validation (preferred) • Experience driving ASIC DFT execution from concept through tapeout (preferred) • Experience working with ATE testers and test teams (preferred) • RTL experience to understand and debugging issues pertaining to DFT (preferred) • Ability to solve complex problems including clock domain crossings (preferred) • Familiar with advanced silicon process and technology nodes for high speed and low power consumption (preferred) • Strong implementation or integration of design blocks using Verilog/System Verilog (preferred)

🏖️ Benefits

• medical, dental and vision insurance • a 401(k) plan with a Cisco matching contribution • paid parental leave • short and long-term disability coverage • basic life insurance • 10 paid holidays per full calendar year • 1 floating holiday for non-exempt employees • 1 paid day off for employee’s birthday • paid year-end holiday shutdown • 4 paid days off for personal wellness • 16 days of paid vacation time per full calendar year • flexible vacation time off program • 80 hours of sick time off provided on hire date • up to 80 hours of unused sick time carried forward • Optional 10 paid days per full calendar year to volunteer