ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead

🔥 3 minutes ago

🌵 Arizona, California, +3 more states – Remote

🌵 Arizona – Remote 🏄 California – Remote 🌲 North Carolina – Remote 🍂 Massachusetts – Remote 🤠 Texas – Remote

💵 $183.8k - $263.6k / year

⏰ Full Time

🟠 Senior

🔧 Hardware Engineer

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Cisco

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1984

🔧 Hardware

🔐 Security

🏢 Enterprise

Hardware • Security • Enterprise

Cisco is a multinational technology company that provides networking hardware, software, and services to enterprises, service providers, and governments. It builds routers, switches, optical transceivers, programmable silicon, and edge computing platforms, and offers security, collaboration (Webex), observability, and AI-enabled software and support services to help organizations design, operate, and secure large-scale networks and data centers. Cisco also delivers professional services, training, and cloud-managed solutions to support digital transformation and AI-ready infrastructure.

📋 Description

• Develop, document, and implement design rules for ultra-high-speed signaling • Analyze substrate signal integrity (SI) and power integrity (PI) • Design, document, and develop ASIC packages for high-volume, high-quality release • Collaborate with system partners, vendors, and design leads • Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments • Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs • Mentor and support the signal integrity team and junior engineers • Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams

🎯 Requirements

• Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, • Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, • PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience. • Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis • Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS. • Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows. • Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.

🏖️ Benefits

• Medical insurance • Dental insurance • Vision insurance • 401(k) plan with a Cisco matching contribution • Paid parental leave • Short and long-term disability coverage • Basic life insurance • 10 paid holidays per full calendar year • 1 floating holiday for non-exempt employees • 1 paid day off for employee’s birthday • Paid year-end holiday shutdown • 4 paid days off for personal wellness • 16 days of paid vacation time per full calendar year (non-exempt employees) • Flexible vacation time off (exempt employees) • 80 hours of sick time off provided on hire date and each January 1st thereafter • Up to 80 hours of unused sick time carried forward from one calendar year to the next • 10 paid days per full calendar year to volunteer