Senior Manager, ASIC Design Engineering

🔥 13 hours ago

🏄 California – Remote

🏄 California – Remote

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

🦅 H1B Visa Sponsor

This company has sponsored H1B visas in the past.

👻 Ghost score 15%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

Apply Now

Find Similar Remote Jobs

Set Up Email Alert For New Jobs

📊 Check your resume score for this job

Improve your chances of getting an interview by checking your resume score before you apply.

Upload Resume

Cornelis Networks

WebsiteLinkedInAll Job Openings

51 - 200 employees

🤖 Artificial Intelligence

🔧 Hardware

🏢 Enterprise

💰 $29M Series B on 2022-11

Artificial Intelligence • Hardware • Enterprise

Cornelis Networks is a leading provider of intelligent, scalable, high-performance interconnects designed for AI applications. The company specializes in delivering end-to-end purpose-built high-performance fabrics to commercial, scientific, academic, and government organizations. Cornelis Networks’ solutions are aimed at enhancing performance, scalability, and efficiency across hyperscale, cloud AI, and on-premises AI/HPC environments. Their offerings are known for scalable architecture, high bandwidth solutions, and universal compatibility with accelerators and GPUs. Originating as an Intel spin-off, the company is positioned to challenge existing technologies like InfiniBand and Ethernet, providing advanced interconnects that power modern AI infrastructure.

📋 Description

• Lead and grow the RTL design engineering team • Report to the VP of ASIC Engineering and work with executive leadership • Manage a team of design engineers • Drive full-lifecycle development of next-generation, high-performance networking ASICs • Build and drive RTL implementation schedules across all SoC subsystems and full-chip milestones • Apply hands-on ASIC RTL design implementation expertise, methodologies, and SoC flows from microarchitecture definition through RTL delivery and tape-out readiness • Coordinate cross-functional execution with Architecture, Design Verification, Emulation, and Physical Design • Own ASIC RTL delivery schedules by tracking, monitoring, and reporting progress against committed plans • Use data-driven insights to predict schedule risks and proactively reallocate human resources • Align RTL delivery schedules with DV and emulation enablement • Manage feedback loops and dependencies • Facilitate physical design handoffs with high-quality RTL and constraints • Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones • Lead long-term headcount planning and organizational design for the ASIC department • Identify skill gaps and execute global talent acquisition strategies supporting the product roadmap • Build a nimble, efficient, world-class design team

🎯 Requirements

• 15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes • At least 5 years in people management • B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience • Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams • Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints • Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies • Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink • Demonstrated ability to optimize designs for PPA (power, performance, area) and integrate major subsystems (interconnect, I/O, memory) • Preferred: Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration • Preferred: Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment

🏖️ Benefits

• Equity, cash, and incentives • Health benefits • Retirement benefits • Medical coverage • Dental coverage • Vision coverage • Disability insurance • Life insurance • Dependent care flexible spending account • Accidental injury insurance • Pet insurance • Generous paid holidays • 401(k) with company match • Open Time Off (OTO) for regular full-time exempt employees • Sick time • Bonding leave • Pregnancy disability leave • Dynamic, flexible work environment • Performance-based incentives, including an annual bonus or sales incentives (depending on role)