Senior Manager, ASIC Design Engineering

🔥 18 minutes ago

🏄 California – Remote

🏄 California – Remote

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

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Cornelis Networks

WebsiteLinkedInAll Job Openings

51 - 200 employees

🤖 Artificial Intelligence

🔧 Hardware

🏢 Enterprise

💰 $29M Series B on 2022-11

Artificial Intelligence • Hardware • Enterprise

Cornelis Networks is a leading provider of intelligent, scalable, high-performance interconnects designed for AI applications. The company specializes in delivering end-to-end purpose-built high-performance fabrics to commercial, scientific, academic, and government organizations. Cornelis Networks’ solutions are aimed at enhancing performance, scalability, and efficiency across hyperscale, cloud AI, and on-premises AI/HPC environments. Their offerings are known for scalable architecture, high bandwidth solutions, and universal compatibility with accelerators and GPUs. Originating as an Intel spin-off, the company is positioned to challenge existing technologies like InfiniBand and Ethernet, providing advanced interconnects that power modern AI infrastructure.

📋 Description

• Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans • Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track • Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently • Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations • Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones • Lead long-term headcount planning and organizational design for the ASIC department • Identify skill gaps and execute global talent acquisition strategies that support the product roadmap

🎯 Requirements

• 15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management • B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience • Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams • Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints • Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies • Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)

🏖️ Benefits

• Competitive compensation package that includes equity, cash, and incentives • Health and retirement benefits • Generous paid holidays • 401(k) with company match • Open Time Off (OTO) for regular full-time exempt employees • Sick time, bonding leave, and pregnancy disability leave