Senior Staff Digital Design Engineer

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University of Washington, Department of Electrical & Computer Engineering

WebsiteLinkedInAll Job Openings

501 - 1000 employees

Founded 1905

📚 Education

🔬 Science

Education • Engineering • Science

University of Washington, Department of Electrical & Computer Engineering is an academic department that focuses on advancing education and research in electrical and computer engineering. It provides a range of undergraduate and graduate programs, emphasizes innovation in engineering, and conducts cutting-edge research in various fields such as microelectronics, robotics, and quantum technology. The department fosters a diverse and inclusive community and offers numerous opportunities for students to engage in hands-on learning, research, and collaboration with industry leaders.

📋 Description

• Drive digital design of next-generation RAIN RFID Reader ICs from architecture through tapeout and silicon validation • Develop micro-architectures, executable models, and RTL for complex digital and mixed-signal IC subsystems • Collaborate with chip architects and RF/analog engineers on mixed-signal architectures, digital control loops, calibration engines, and analog-IP interface logic • Partner with physical design and verification teams on timing closure, signal integrity, and production-ready Reader IC delivery • Define and implement DFT strategies, including scan insertion, BIST, and boundary scan • Work with CAD/EDA engineers to evolve ASIC/SoC design flows, methodologies, and best practices • Enhance existing RAIN RFID Reader products with features, performance improvements, and power optimizations • Support post-silicon bring-up and debugging by correlating RTL and simulation results with lab measurements

🎯 Requirements

• Bachelor’s degree in Computer Engineering with 12 years of experience, or 8 years with an MS, or 5 years with a PhD, required • 12+ years of RTL design experience • At least 2–3 full tapeout cycles, preferably on mixed-signal or RF-integrated ICs • Strong skills in digital logic design, micro-architecture definition, synthesis, and timing closure • Proficiency in Verilog and SystemVerilog for RTL development, behavioral modeling, and verification • Understanding of CDC analysis, clock gating, low-power design (UPF/CPF), and static timing analysis • Experience with UVM-based verification, functional coverage, assertion-based verification, and DFT implementation (scan, MBIST, ATPG) • Scripting proficiency in Python, Perl, or UNIX shell • Ability to lead technical workstreams, mentor junior engineers, and communicate across analog, digital, and systems disciplines • Compliance with applicable U.S. export control requirements; additional national-identity documentation may be required

🏖️ Benefits

• Additional rewards may include merit increases, annual bonus and stock • Sales incentives may be available for certain roles • Healthcare benefits for US-based employees • 401(k) plan and company match • Competitive benefits • Support for remote work • Weekly Q&A sessions with the executive team • Open paid-time-off policy • Work/life balance support • Reasonable accommodation for individuals with disabilities