Principal ASIC Physical Design Engineer

🔥 4 minutes ago

🇺🇸 United States – Remote

💵 $190k - $280k / year

⏰ Full Time

🔴 Lead

🧑‍🔧 Mechanical Engineer

👻 Ghost score 21%

What it means: the chance that no one is really hiring for this job.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.Why this score:

• Just posted.
• Jobs at this company usually fill in 55 days.
• 17 open roles for a team of 34.

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K2 Space Corporation

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🎖️ Defense

📦 Logistics

🏭 Manufacturing

Defense • Logistics • Manufacturing

K2 Space Corporation is a California-based aerospace manufacturer that designs and produces large, high-power satellite buses intended to deliver significantly more power, mass and payload volume at lower cost than traditional large satellites. The company emphasizes production-line style builds and commercial supply chains to shorten lead times and reduce per-unit cost, enabling multi-manifest launches and multi-orbit missions across LEO, MEO, GEO and cislunar space. K2 serves commercial, scientific and government/defense customers, and focuses on enabling missions that require high throughput, high-power payloads.

📋 Description

• Lead implementation of complex SoCs for next-generation satellite and space systems • Own the complete RTL-to-GDSII flow, including synthesis, floorplanning, place & route, CTS, STA, physical verification, and sign-off • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area • Collaborate with front-end, RTL design, DFT, verification, architecture, packaging, test, and post-silicon teams • Drive timing closure across multiple voltage and process corners using foundry-qualified tools • Partner on package-aware floorplanning, signal/power integrity, and chip-to-board integration • Manage and technically guide external physical design partners and service vendors • Work with EDA vendors to debug and optimize tool flows and evaluate methodologies • Support chip bring-up and debug • Support the product through production and spaceflight • Develop and implement new SoC subsystems for satellite communications and beyond • Contribute to cutting-edge SoCs that will fly in space

🎯 Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field • 10+ years of experience in ASIC physical design for high-performance SoCs • End-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools • Hands-on experience with timing closure, IR drop analysis, and ECO implementation • Understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs • Experience with advanced FinFET process nodes • Experience managing or coordinating offshore/outsourced physical design teams or vendors • Familiarity with DFT integration, STA sign-off, and power domain implementation using UPF/CPF • Excellent communication, leadership, and cross-functional collaboration skills • Ability to act as a technical leader and subject-matter expert, teaching, growing, and mentoring team members • Must be a U.S. Person as defined by ITAR or otherwise eligible for a federally issued export control license

🏖️ Benefits

• Equity in the company • Paid time off • Medical coverage • Dental coverage • Vision coverage • Life insurance • Paid parental leave • Comprehensive benefits package • Other perks

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