Principal ASIC Physical Design Engineer

🕒 July 1

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K2 Space Corporation

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🚀 Aerospace

🔧 Hardware

🏛️ Government

Aerospace • Hardware • Government

K2 Space Corporation is a California-based aerospace manufacturer that designs and produces large, high-power satellite buses intended to deliver significantly more power, mass and payload volume at lower cost than traditional large satellites. The company emphasizes production-line style builds and commercial supply chains to shorten lead times and reduce per-unit cost, enabling multi-manifest launches and multi-orbit missions across LEO, MEO, GEO and cislunar space. K2 serves commercial, scientific and government/defense customers, and focuses on enabling missions that require high throughput, high-power payloads.

📋 Description

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off. • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA). • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration. • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools. • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration. • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards. • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. • Support chip bring-up and debug through close collaboration with post-silicon and test teams. • Support your product through production and spaceflight.

🎯 Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field • 10+ years of experience in ASIC physical design for high-performance SoCs • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens) • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs • Experience with advanced FinFET process nodes • Prior experience managing or coordinating offshore/outsourced PD teams or vendors • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF) • Excellent communication, leadership, and cross-functional collaboration skills. • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

🏖️ Benefits

• Comprehensive benefits package including paid time off • Medical/dental/vision coverage • Life insurance • Paid parental leave • Equity in the company