Senior DFT Engineer

🕒 March 12

🌵 Arizona, Colorado, +2 more states – Remote

🌵 Arizona – Remote ⛰️ Colorado – Remote 🐊 Florida – Remote 🌲 North Carolina – Remote

💵 $136k - $218.5k / year

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

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NVIDIA

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1993

🤖 Artificial Intelligence

🎮 Gaming

Artificial Intelligence • Gaming • Automotive

NVIDIA is a leading technology company specializing in accelerated computing and artificial intelligence. NVIDIA pioneers advancements in graphical processing units (GPUs), cloud computing, data centers, and virtual reality, with a focus on gaming, automotive, healthcare, and robotics industries. The company's innovations, such as NVIDIA Omniverse, transform traditional digital processes by enabling high-fidelity simulations and rendering tasks. Their applications span various industries, from autonomous vehicles using NVIDIA DRIVE to healthcare solutions with NVIDIA Clara, and AI-driven analytics and workflows.

📋 Description

• Define and implement SCAN, MBIST, and JTAG debug structures, applying sophisticated DFT techniques to drive post-Si testing plans • Drive the creation of ATPG and MBIST test vectors • Build DFT timing constraints and partner with the Physical Design and STA sign-off team to ensure timing closure in DFT mode • Work closely with the post-silicon team to bring up test patterns on silicon, ensuring flawless bringup • Collaborate with the CAD methodology team to introduce innovative and intelligent AI driven optimizations, improving efficiency in DFT implementation

🎯 Requirements

• Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) • 5+ years of industry experience in DFT for high-performance ASICs • Practical experience with SCAN/MBIST/Test generation tools and processes for large SoC/ASIC • Domain expertise in DFT techniques such as ATPG, test pattern translation, yield learning, scan compression, MBIST, IEEE 1500 standard, and LBIST • Familiarity with ATPG Streaming SCAN Network (SSN) implementation • Experience with UDFMs like Cell Aware and Small Delay Defect • Consistent track record in yield estimation and test optimization • Experience working with real silicon in the lab and debugging DFT test sequences on ATE to resolve silicon issues • Solid understanding of RTL to GDS methodologies and formal equivalence • Excellent coding skills in Tcl and Python • Outstanding interpersonal and organizational skills with a strong desire to work as part of a team with varied strengths.

🏖️ Benefits

• equity • benefits