Physical Design Engineer – Die-to-Die Interface, RTL to GDSII

🕒 March 18

🇺🇸 United States – Remote

💵 $100k - $500k / year

⏰ Full Time

🟡 Mid-level

🟠 Senior

🧑‍🔧 Mechanical Engineer

👻 Ghost score 32%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Tenstorrent Inc.

WebsiteLinkedInAll Job Openings

51 - 200 employees

Founded 2016

🏭 Manufacturing

💼 Consulting

🤖 Artificial Intelligence

Manufacturing • Consulting • Artificial Intelligence

Tenstorrent is a cutting-edge technology company based in Santa Clara, CA, specializing in AI semiconductors and computing solutions. They have developed advanced products like the TT-QuietBox, a liquid-cooled workstation designed for AI model development, and the Tenstorrent Galaxy, a high-performance AI compute server. Recently, Tenstorrent secured over $693M in Series D funding to enhance its AI chip capabilities and challenge market leaders in the AI data center sector.

📋 Description

• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout. • Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off. • Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS. • Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure. • Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug). • Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.

🎯 Requirements

• A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. • Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off. • Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity). • Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs. • A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

🏖️ Benefits

• Highly competitive compensation package • Health insurance • Professional development opportunities • Equal opportunity employer