Design Verification Architect

🔥 1 hour ago

🏄 California – Remote

🏄 California – Remote

💵 $150k - $300k / year

⏰ Full Time

🟠 Senior

🔴 Lead

🏛️ Architect

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TYLsemi

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2026

🔧 Hardware

🤖 Artificial Intelligence

🤝 B2B

Hardware • Artificial Intelligence • B2B

TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functions—XPUs, switches, connectivity, power, and system scaling—and it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.

📋 Description

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP → subsystem → full SoC level • Architect and develop reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs • Establish methodologies for seamless reuse and portability, including Portable Stimulus (PSS)-based verification flows • Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM) • Drive multi-level verification strategies, enabling efficient scaling across: Block-level, Multi-block/subsystem level, Full-chip SoC level • Define and enforce verification quality metrics, coverage closure strategies, and sign-off criteria • Champion a “fail-fast” philosophy to detect issues early and improve overall design quality • Drive initiatives toward first-pass silicon success, minimizing escapes and post-silicon debug effort • Leverage AI/ML techniques and AI agents to: Automate testbench generation, Improve stimulus generation and coverage closure, Enhance regression efficiency and debug productivity, Enable intelligent verification QA and anomaly detection • Collaborate closely with design, architecture, physical design, and software teams to ensure alignment and early issue detection • Mentor and guide DV teams on best practices, methodology adoption, and architectural decisions.

🎯 Requirements

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field • 12+ years of experience in Design Verification, with significant exposure to large SoC verification • Proven experience in defining and deploying verification architectures for complex chips • Strong expertise in: SystemVerilog and UVM • Coverage-driven verification (functional + code coverage) • Assertion-based verification (SVA) • Hands-on experience with Portable Stimulus (PSS) and cross-level stimulus reuse • Deep understanding of SoC architectures in AI, HPC, or Networking domains • Experience with multi-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement • Strong debugging skills and ability to handle complex system-level issues.

🏖️ Benefits

• No Politics, No Bureaucracy • Remote-Friendly, Global Team • Move Fast, Ship Real Products • Ownership mindset. • Bias for action. • Deep technical expertise. • Low ego, high standards.