
11 - 50 employees
Founded 2026
π§ Hardware
π€ Artificial Intelligence
π€ B2B
Hardware β’ Artificial Intelligence β’ B2B
TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functionsβXPUs, switches, connectivity, power, and system scalingβand it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.
π₯ 13 minutes ago
π California β Remote
π΅ $175k - $350k / year
β° Full Time
π΄ Lead
π§βπ§ Mechanical Engineer
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11 - 50 employees
Founded 2026
π§ Hardware
π€ Artificial Intelligence
π€ B2B
Hardware β’ Artificial Intelligence β’ B2B
TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functionsβXPUs, switches, connectivity, power, and system scalingβand it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.
β’ Own end-to-end analog block development: requirements definition, architecture, transistor-level design, simulation, and signoff β’ Design and optimize analog/mixed-signal circuits such as amplifiers, references, biasing, regulators (LDO/DC-DC support), comparators, oscillators/clocking, data converters (as applicable), and sensor/AFE front ends β’ Drive performance across PVT corners, mismatch/Monte Carlo, aging/reliability considerations, and realistic loading/interaction with surrounding blocks β’ Partner with layout to guide floorplanning, matching/guarding strategies, parasitic-aware design, and post-layout closure (PEX) β’ Develop and maintain testbenches, modeling collateral, and documentation to enable efficient verification and integration β’ Support silicon bring-up and debug: correlate lab data to simulations, root-cause issues, and implement design fixes or ECOs β’ Collaborate cross-functionally with digital, firmware, DFT, validation, and product engineering to ensure system-level success β’ Contribute to design methodology improvements: reusable circuits, checklists, signoff flows, and best practices that scale across programs
β’ 5+ years of experience in analog or mixed-signal IC design β’ Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems β’ Proficiency with industry-standard EDA tools and simulation flows (e.g., Spectre/HSPICE, ADE, waveform/debug tooling) β’ Experience closing designs through post-layout parasitics and across process/voltage/temperature corners β’ Ability to translate ambiguous system needs into clear block requirements and executable design plans β’ Strong debugging skills and comfort working with lab/validation teams to correlate silicon to simulation β’ Clear communication and high ownership in cross-site, cross-functional environments
β’ No Politics, No Bureaucracy β’ Remote-Friendly, Global Team β’ Move Fast, Ship Real Products
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