Synthesis or Formal Verification Developer

Job not on LinkedIn

🔥 0 minutes ago

🌏 Anywhere in the World

💵 €6k / month

⏳ Contract/Temporary

🟡 Mid-level

🟠 Senior

🖥 Software Engineer

👻 Ghost score 6%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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YosysHQ

WebsiteLinkedInAll Job Openings

1 - 10 employees

🔧 Hardware

Hardware

YosysHQ is the team behind Yosys and related Open Source EDA (Electronic Design Automation) projects, offering commercial products and services. They focus on providing solutions that enhance the design process in electronics engineering and support the development of tools for hardware design.

📋 Description

• Contribute to YosysHQ’s synthesis or formal verification focus areas • Develop and maintain open-source EDA tools and software packages • Work on formal verification tools using C++, Rust, and Python • Implement hardware model checking and related formal methods • Develop synthesis functionality using C++ and RTL hardware design knowledge • Work on custom development of individual features and complete flows based on YosysHQ software components • Support and train users and developers working with the software • Independently take responsibility for assigned tasks and resolve challenges • Participate in team meetings typically held between 3pm and 6pm Vienna time (CET/CEST)

🎯 Requirements

• Comfortable with C++ or Rust for formal verification; willingness to learn the other languages and Python • Familiarity with implementation of hardware model checking, or background in verification/formal methods such as SAT/SMT solving, automated/interactive theorem proving, programming language theory, or automata theory • Some contact with RTL hardware design for formal verification • Comfortable with C++ for synthesis • Some experience with RTL hardware design, ideally for ASIC • Transferable experience building software for engineering or science applications, implementing algorithms from scientific literature, or working on a compiler • Experience becoming familiar with a large pre-existing project • Ability to take responsibility, work independently, and address challenges without extensive supervision • Must not live in a country subject to sanctions or export restrictions, or be banned from performing work for the US government • CV and brief cover letter required for application

🏖️ Benefits

• Flexible remote work from wherever you are • Flexible schedule; choose when to work outside team meetings • Part-time option of 1–5 days per week • Flat pay hierarchy with the same rate for everyone • Opportunity to work on open-source EDA projects • Work with synthesis and formal verification technologies • Support and training for users and developers of software packages