Senior RTL Design Engineer

Job not on LinkedIn

🕒 July 13

🇺🇦 Ukraine – Remote

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

👻 Ghost score 34%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Capgemini

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1967

💼 Consulting

🏥 Healthcare

📦 Logistics

Consulting • Healthcare • Logistics

Capgemini is a global leader in partnering with businesses to transform and manage their operations by harnessing the power of technology. With expertise across a wide array of industries such as aerospace, automotive, banking, and healthcare, Capgemini provides a constantly evolving portfolio of services to meet the ever-changing needs of their clients. Their offerings include cloud, cybersecurity, data and artificial intelligence, and enterprise management, among others. Capgemini also emphasizes innovation and sustainability, helping companies achieve digital transformation while promoting environmental and social responsibility. Additionally, Capgemini provides career opportunities across various levels and professions, encouraging innovation and diversity in its workforce.

📋 Description

• Own feasibility studies for defining system architecture, requirements, and external interfaces • Develop microarchitecture and RTL design with architecture and functional teams from specification through tape-out • Perform RTL coding, linting, CDC/RDC analysis, and development of timing constraint files (SDC) • Execute and manage CDC/RDC verification activities at IP, subsystem, and SoC levels • Review RTL implementations and investigate tool-reported violations • Identify root causes and distinguish genuine design issues from false positives through waiver definition • Define and maintain CDC/RDC constraints (SDC/SGDC), verification environments, and SoC operating modes • Develop, automate, and improve CDC/RDC verification flows using Synopsys VC Static CDC/RDC tools • Define and implement methodologies for automatic generation of IP abstraction models • Run and analyze CDC/RDC verification scenarios across use cases and operating modes • Collaborate with RTL designers and IP owners on architectural and RTL solutions for CDC/RDC issues • Verify implementation fixes and ensure closure of CDC/RDC sign-off criteria • Collaborate with Synthesis, STA, Physical Design, DFT, and Verification teams to achieve functional, timing, power, and area targets • Develop design methodologies, automation scripts, and engineering tools to improve productivity and design quality

🎯 Requirements

• 8+ years of experience in VLSI design • BSc/MSc in Electrical or Computer Engineering • Strong Verilog/SystemVerilog or VHDL skills • Experience defining microarchitecture and designing complex digital blocks and subsystems • Strong SoC design experience • Proficiency in Lint, CDC, RDC, and Low Power Design methodologies • Experience with backend flows, including synthesis and static timing analysis (STA) • Familiarity with CPU architectures and instruction sets: ARM, RISC-V, or x86 • Experience with Python, Perl, or C • Understanding of modern verification methodologies and design sign-off flows • Experience with Synopsys VC Static CDC/RDC or equivalent verification tools is an advantage • Strong analytical, debugging, communication, and collaboration skills

🏖️ Benefits

• Health insurance from the first days, regardless of the probationary period • Christmas holidays from December 25 to December 31 • Psychological counseling provided by the Veteran Hub • Internal policy making the company friendly to military and veterans