Senior DFT Engineer

Job not on LinkedIn

🔥 1 hour ago

🇵🇱 Poland – Remote

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 19%

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Commit

WebsiteLinkedInAll Job Openings

501 - 1000 employees

🔒 Cybersecurity

Cybersecurity

Commit is a global tech services company founded in 2005, with a presence in Israel, the US, Canada, the UK, and Europe. It specializes in advanced technologies and applications, providing innovative, end-to-end technology solutions, including custom software and IoT platforms. Commit has over 700 multidisciplinary experts who cater to a wide array of companies, from startups to large enterprises, and focuses on areas like Cloud, GenAI, Software, IoT, Big Data, Cybersecurity, and data center migration. Its proprietary Flexible R&D methodology supports clients in transforming their technology visions into high-quality products while reducing costs and improving time-to-market.

📋 Description

• Own Design-for-Test for customer SoCs end-to-end • Define and implement DFT architecture • Handle scan and ATPG, including pattern generation and validation • Implement memory BIST and boundary scan • Perform pattern validation through gate-level simulation • Conduct DFT DRC analysis and debug test coverage • Improve test coverage across required fault models • Own DFT flow from concept through tape-out and production test hand-off • Automate flows using Perl, Tcl, UNIX scripting, and potentially Python • Support production test hand-off

🎯 Requirements

• BSc in Electrical Engineering from a recognized university • Minimum 3 years of hands-on DFT experience — must; senior-level profiles preferred • Knowledge of scan, ATPG, at-speed test, memory BIST, and I/O DFT methodologies • Experience with scan insertion and ATPG for stuck-at, transition-delay, bridging, and IDDQ fault models • Experience improving test coverage • Experience with DFT DRC analysis and coverage debugging using Synopsys DFT Compiler, TestMAX (TetraMAX), SpyGlass DFT, or equivalent Siemens (Mentor) Tessent tools • Experience with Tessent MBIST • Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6, and IEEE 1500 (formerly P1500) • Hands-on design and implementation of DFT features • End-to-end DFT flow ownership from concept through tape-out to production • Experience setting up and running gate-level simulations for pattern validation • Experience with formal equivalence checking • Perl, Tcl, and UNIX scripting for flow automation • Nice to have: broader Siemens Tessent experience, including ScanPro, TestKompress, and LBIST • Nice to have: advanced-node experience at 7nm and below • Nice to have: Python for flow automation