
1001 - 5000 employees
Founded 1983
🏭 Manufacturing
📣 Marketing
🤖 Artificial Intelligence
Manufacturing • Marketing • Artificial Intelligence
Altera is a company focused on transforming the fashion industry through advanced technology and artificial intelligence. By utilizing AI, they enable businesses to create personalized clothing experiences, tailoring designs to individual customer preferences. Their approach enhances the online buying experience, improving customization options and transforming how designs are developed and marketed in the apparel sector.
🕒 September 11
Where this job comes from
Posted on Altera's careers page, not through a job board
First seen by Remote Rocketship September 11
Still open on Altera's site. Checked 3 hours ago.

1001 - 5000 employees
Founded 1983
🏭 Manufacturing
📣 Marketing
🤖 Artificial Intelligence
Manufacturing • Marketing • Artificial Intelligence
Altera is a company focused on transforming the fashion industry through advanced technology and artificial intelligence. By utilizing AI, they enable businesses to create personalized clothing experiences, tailoring designs to individual customer preferences. Their approach enhances the online buying experience, improving customization options and transforming how designs are developed and marketed in the apparel sector.
• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks • Write testbenches, functional coverage models, and assertions • Run simulations, analyze failures, and debug both RTL and testbench issues • Collaborate with design, architecture, and analog teams on block-level and top-level verification • Verify high-speed SerDes IP used in PCIe, Ethernet, and other industry-standard interfaces
• BSc in Electrical Engineering, Computer Engineering, or equivalent • 0–5 years of experience in digital design or verification (internships, academic projects, or industry) • Working knowledge of SystemVerilog and basic familiarity with UVM concepts • Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing • Strong analytical and debug mindset — you enjoy getting to the bottom of a problem • Good communication skills in English (spoken and written) • Candidates should preferably be able to reside in Iași
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