Senior ASIC Design Engineer

🔥 0 minutes ago

🏄 California – Remote

🏄 California – Remote

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

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👻 Ghost score 12%

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Cornelis Networks

WebsiteLinkedInAll Job Openings

51 - 200 employees

🤖 Artificial Intelligence

🔧 Hardware

🏢 Enterprise

💰 $29M Series B on 2022-11

Artificial Intelligence • Hardware • Enterprise

Cornelis Networks is a leading provider of intelligent, scalable, high-performance interconnects designed for AI applications. The company specializes in delivering end-to-end purpose-built high-performance fabrics to commercial, scientific, academic, and government organizations. Cornelis Networks’ solutions are aimed at enhancing performance, scalability, and efficiency across hyperscale, cloud AI, and on-premises AI/HPC environments. Their offerings are known for scalable architecture, high bandwidth solutions, and universal compatibility with accelerators and GPUs. Originating as an Intel spin-off, the company is positioned to challenge existing technologies like InfiniBand and Ethernet, providing advanced interconnects that power modern AI infrastructure.

📋 Description

• Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic • Collaborate with verification engineers to create block- and system-level test plans • Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure • Support post-silicon validation with hardware, firmware, and software teams to debug and resolve ASIC issues • Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems • Develop world-class SoCs for high-performance computing, advanced data analytics, and AI interconnect solutions

🎯 Requirements

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field • 8+ years of post-college experience in digital design • Proficiency in Verilog and SystemVerilog • Experience in RTL design for high-speed data paths or packet processing in ASICs • Deep understanding of Host Ethernet adaptor architectures • Familiarity with timing closure and modern physical design methodologies • Proven ability in system-level debug and root cause analysis of technical issues • Strong verbal and written communication skills • Knowledge of Ethernet architecture and networking protocols • Prior experience with RTL development for Ethernet host adapters and system debug • Expertise in multiple clock domain designs and asynchronous interfaces • 5+ years of experience with scripting languages such as TCL, Python, or Perl • Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime

🏖️ Benefits

• Equity, cash, and incentives • Health, medical, dental, and vision coverage • Disability and life insurance • Dependent care flexible spending account • Accidental injury insurance • Pet insurance • Generous paid holidays • 401(k) with company match • Open Time Off (OTO) for regular full-time exempt employees • Sick time • Bonding leave • Pregnancy disability leave • Flexible work environment