Physical Design Engineer

🔥 12 hours ago

🇺🇸 United States – Remote

💵 $180k - $260k / year

⏰ Full Time

🟠 Senior

🔴 Lead

🧑‍🔧 Mechanical Engineer

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Delos Data

WebsiteLinkedInAll Job Openings

11 - 50 employees

🏭 Manufacturing

💼 Consulting

📦 Logistics

Manufacturing • Consulting • Logistics

Delos Data is a company of software, system, and silicon experts building specialized interconnects and infrastructure optimized for AI inference. They focus on distributing compute and memory efficiently to make inference faster and more responsive, offering real-time visibility into always-on AI infrastructure and positioning their technology for enterprise AI deployments. Delos emphasizes inference-specific networking and hardware design rather than repurposing HPC or cloud training solutions, and they engage with the AI community at events like NVIDIA GTC.

📋 Description

• Serve as an early member of the physical design team • Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff • Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability • Develop and optimize power-grid implementations and support IR-drop and electromigration closure • Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation • Own setup, hold, signal-integrity, congestion, and physical implementation problems • Lead timing closure across block boundaries and support top-level timing convergence • Perform and drive static timing analysis across multiple modes and corners • Support signal-integrity analysis and assess timing impact from crosstalk, variation, and physical effects • Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements • Perform or support static and dynamic IR-drop and electromigration analysis • Develop implementation strategies for high-performance and physically challenging design portions • Partner with RTL and architecture teams to identify implementation problems and recommend architectural or logical changes • Collaborate with DFT, verification, package, SI/PI, and other engineering teams on cross-functional design issues • Develop and improve physical design flows, scripts, automation, metrics, and methodologies • Evaluate implementation results and improve PPA, runtime, convergence, and design quality • Provide technical guidance and mentorship to physical design engineers • Participate in design reviews, methodology reviews, and tapeout readiness assessments • Serve as a technical escalation point for complex physical design and signoff issues

🎯 Requirements

• 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts • Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification • Strong expertise in static timing analysis and multi-mode, multi-corner timing closure • Strong understanding of power delivery, IR drop, electromigration, and signal integrity • Demonstrated ability to independently own complex blocks or major portions of a chip through signoff • Strong understanding of clock design, timing constraints, variation, extraction, and advanced-node physical effects • Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools • Strong scripting and automation skills using Tcl, Python, Perl, or similar languages • Ability to debug complex design problems across RTL, timing, physical implementation, and signoff domains • Strong communication skills and ability to provide technical leadership without requiring formal management authority • Experience with advanced process nodes • Experience with large, high-frequency or highly interconnected semiconductor designs • Experience with hierarchical design and top-level physical integration • Experience developing physical design methodologies and automation • Experience working closely with package, SI/PI, and power-delivery teams • Experience with multi-die, chiplet, or advanced packaging architectures • Familiarity with EDA tool evaluation, benchmarking, and optimization • Experience in an early-stage semiconductor environment • Ability to independently drive complex technical problems to closure • Comfortable operating across both detailed implementation work and broader chip-level design considerations • Ability to work effectively in a highly collaborative, fast-paced engineering organization • Must be authorized to work in the United States

🏖️ Benefits

• Meaningful equity • Benefits • 401(k)