RTL Design Engineer

🔥 14 hours ago

🏄 California – Remote

🏄 California – Remote

💵 $160k - $240k / year

⏰ Full Time

🟡 Mid-level

🟠 Senior

🧑‍🔧 Mechanical Engineer

👻 Ghost score 3%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Delos Data

WebsiteLinkedInAll Job Openings

11 - 50 employees

🏭 Manufacturing

💼 Consulting

📦 Logistics

Manufacturing • Consulting • Logistics

Delos Data is a company of software, system, and silicon experts building specialized interconnects and infrastructure optimized for AI inference. They focus on distributing compute and memory efficiently to make inference faster and more responsive, offering real-time visibility into always-on AI infrastructure and positioning their technology for enterprise AI deployments. Delos emphasizes inference-specific networking and hardware design rather than repurposing HPC or cloud training solutions, and they engage with the AI community at events like NVIDIA GTC.

📋 Description

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog • Translate architectural specifications into clean, efficient, and scalable microarchitectures • Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure • Develop high-quality, reusable RTL with strong coding standards and documentation • Perform linting, CDC analysis, and ensure synthesis readiness of designs • Support integration and debug of RTL in simulation and early silicon environments • Participate in design reviews and provide technical input on architecture and implementation tradeoffs • Work with verification teams to ensure comprehensive functional coverage • Assist in timing closure and support backend teams as needed • Contribute to continuous improvement of design methodologies, flows, and tools

🎯 Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field • 5+ years of experience in RTL design • Strong hands-on experience with Verilog/SystemVerilog • Solid understanding of synchronous digital design and microarchitecture principles • Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE) • Familiarity with synthesis, timing, and physical design constraints • Strong analytical and problem-solving skills • Clear written and verbal communication skills for cross-functional collaboration • High attention to detail and ability to deliver high-quality design outcomes • Ability to work independently and manage tasks to completion, including AI-assisted workflows • Authorized to work in the United States

🏖️ Benefits

• Meaningful equity • Benefits • 401(k)