Senior ASIC Physical Design Engineer

Job not on LinkedIn

🕒 August 5

🇺🇸 United States – Remote

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

👻 Ghost score 29%

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Niobium Microsystems

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11 - 50 employees

🏭 Manufacturing

💼 Consulting

🏥 Healthcare

💰 $90k Grant on 2021-11

Manufacturing • Consulting • Healthcare

Niobium Microsystems is a company revolutionizing the field of data privacy and zero trust computing by offering FHE (Fully Homomorphic Encryption) solutions. They have developed the industry's first purpose-built FHE hardware accelerator, a PCIe card that significantly enhances the performance of FHE software across all major schemes, supporting seamless integration into various applications such as cloud computing, fraud detection, and medical research. Their technology guarantees the privacy of data even during processing, ensuring that sensitive information remains secure. Niobium partners with leading organizations to bring guaranteed privacy to generative AI applications and pushes for standards in quantum-resilient cryptography.

📋 Description

• Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery • Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow • Architect and execute floorplanning strategies for large, hierarchical SoCs • Integrate IPs and macros and define physical partitions and hierarchy • Develop power grid architecture and clock distribution topology • Define die size, aspect ratio, and physical constraints • Collaborate with Architecture and RTL teams on physical feasibility, timing closure readiness, and area/power targets • Lead block-level and top-level PnR using Cadence and Synopsys tools • Drive timing convergence across corners, modes, voltage domains, and operating conditions • Optimize PPA, mitigate congestion, and ensure physical integrity • Implement CTS and optimize skew, latency, and clock power • Lead IR/EM sign-off strategy, thermal analysis, and full-chip physical verification including DRC/LVS/ERC • Integrate and validate low-power methodologies, including UPF/CPF flows • Partner with DFT and PD teams on scan insertion, BIST structures, and test modes • Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing • Set physical design quality standards, conduct design reviews, and ensure execution through tapeout • Provide technical leadership to junior and mid-level physical designers • Mentor, coach, and guide engineers in methodology, debugging, and best practices • Champion continuous improvement across flows, scripts, and design methodology

🎯 Requirements

• 8+ years of relevant experience in ASIC Physical Design • Strong track record of multiple tape-outs at advanced technology nodes (16nm → 3nm preferred) • BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field • Deep expertise in floorplanning, place & route, CTS, STA/timing closure, physical verification & sign-off, and low power design and UPF • Strong hands-on proficiency with Cadence and/or Synopsys physical design toolchains • Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities • Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans • Strong communication skills • Highly motivated, proactive, and able to operate effectively in a distributed team environment • Comfortable owning schedules, deliverables, and quality in a fast-moving development cycle • Exceptional analytical, debugging, and problem-solving skills with meticulous attention to detail

🏖️ Benefits

• Competitive salaries • Equity in the form of Incentive Stock Options (ISO) • Employer paid medical insurance plan • Health Savings Account (HSA) with employer contributions • Dental and vision reimbursement account (HRA) • 401(k) retirement plan with employer match • Flexible work location with remote options • Flexible time off

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