ASIC/SoC Design & Verification Engineer

Job not on LinkedIn

🕒 July 29

🇺🇸 United States – Remote

💵 $70 - $100 / hour

⏱ Part Time

🟡 Mid-level

🟠 Senior

✍️ Designer

👻 Ghost score 24%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Weekday (YC W21)

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2021

💼 Consulting

👥 HR Tech

☁️ SaaS

Consulting • HR Tech • SaaS

Weekday is a modern recruitment platform that combines AI technologies with a vast database of potential candidates, aiming to streamline the hiring process for companies in India. They offer various services, including a proactive outreach approach that helps employers connect with top talent, as well as tools for candidates to easily apply for jobs. Weekday's emphasis on candidate engagement through multiple channels, including email, WhatsApp, and phone calls, sets it apart in the competitive landscape of recruitment agencies.

📋 Description

• Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience. • Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog. • Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback. • Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs. • Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks. • Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.

🎯 Requirements

• Hands-on experience in **ASIC and/or SoC design**, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects. • Strong proficiency in **SystemVerilog** and **Verilog**. • Experience working with industry-standard EDA tools such as **Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi**, or equivalent open-source tools including **Icarus Verilog, Verilator, Cocotb, Yosys,** and **OpenROAD**. • Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow. • Deep expertise in one or more of the following areas: • - RTL Design and Microarchitecture • - Functional Verification (UVM, SVA, Cocotb, testbench development) • - IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems) • - Formal Verification and Coverage Closure • - Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization • - Analog/Mixed-Signal Design Verification • - Hardware Specification Development and Technical Documentation • Ability to commit **20–40 hours per week** with reliable weekday availability. • Strong written communication skills and the ability to work independently in a remote environment.