
5001 - 10000 employees
Founded 1985
📡 Telecommunications
🔧 Hardware
💰 Series C on 1995-12
Telecommunications • Hardware • Networking
Ciena is a global leader in optical and routing systems, services, and automation software. We build the world’s most adaptive networks to address ever-increasing digital demands for richer, more connected experiences for all users. For three-plus decades, we’ve brought our innate sense of humanity to our relentless pursuit of innovation.
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5001 - 10000 employees
Founded 1985
📡 Telecommunications
🔧 Hardware
💰 Series C on 1995-12
Telecommunications • Hardware • Networking
Ciena is a global leader in optical and routing systems, services, and automation software. We build the world’s most adaptive networks to address ever-increasing digital demands for richer, more connected experiences for all users. For three-plus decades, we’ve brought our innate sense of humanity to our relentless pursuit of innovation.
• Own schematic-level design and post-layout verification of the transmitter signal chain and its blocks: DAC-based output stage, serialization, clocking interface, and output driver • Work closely with management, system designers, and lab validation teams to evolve the architecture and meet standard and product requirements • Evaluate circuit topologies and recommend implementations based on tradeoffs across power, area, bandwidth, and technology constraints. • Collaborate with layout and design engineers to deliver designs through full GDSII integration. • Drive extraction-based post-layout simulations and validate transmitter performance (bandwidth, linearity/RLM, return loss, jitter, and power) across process, voltage, and temperature conditions. • Own root-cause analysis of design- and post-layout performance gaps and implement the corrective design actions to meet specifications. • Maintain block- and transmitter-level performance and power tracking against the agreed targets. • Translate agreed architecture and system requirements into the transmitter implementation, and feed design and silicon learnings back to inform the next architecture step. • Build and use behavioral/design models (e.g., MATLAB, Verilog-A) to support topology tradeoffs and specification alignment. • Partner with lab validation teams to correlate silicon results with simulations and support test-chip, product bring-up and characterization. • Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular basis.
• Bachelor’s degree in Electrical Engineering or Computer Engineering, or applicable scientific discipline. • 10+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post-layout verification. • Application of transmitter circuit building blocks including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits. • Execution of post-layout and extraction-based simulations to validate performance across process, voltage, and temperature conditions. • Delivery of analog circuit designs through silicon validation. • Utilization of Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR-RC, and MMSIM. • Demonstrated written and verbal communication skills and ability to work independently and within a team environment.
• medical, dental, and vision plans • participation in 401(K) (USA) & DCPP (Canada) with company matching • Employee Stock Purchase Program (ESPP) • Employee Assistance Program (EAP) • company-paid holidays • paid sick leave • vacation time
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