Lead DFT Engineer

🔥 0 minutes ago

🌐 Canada, United States – Remote

🇨🇦 Canada – Remote 🇺🇸 United States – Remote

💵 $200k - $250k / year

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

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EnCharge AI

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2022

🤖 Artificial Intelligence

🔧 Hardware

🤝 B2B

💰 $100M Series B - EnCharge AI on 2025-02

Artificial Intelligence • Hardware • B2B

EnCharge AI is a company that develops analog in-memory computing hardware and complementary software to accelerate on-device and edge-to-cloud AI workloads. Their technology includes the EN100 analog AI accelerator and other form factors (chiplets, ASICs, PCIe cards) designed to deliver much higher energy efficiency, compute density, and lower total cost of ownership for inference compared with conventional GPUs and digital accelerators. EnCharge emphasizes sustainability, data privacy through local processing, and deployment for enterprise and developer customers seeking efficient, scalable AI computation outside traditional cloud infrastructure.

📋 Description

• Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST • Develop In-System Test (IST) and power-on self-test (POST) strategies for chip health in remote edge data centers • Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST • Collaborate with Design, Physical Design, and Yield teams to achieve high test coverage while minimizing area overhead and power impact, including timing analysis • Lead silicon bring-up and debug on ATE to root-cause silicon failures and optimize test time

🎯 Requirements

• 12+ years of experience in DFT, including at least 2 years in a leadership or principal role • Bachelor’s degree in a related field • Mastery of Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus • Deep expertise in MBIST with repair capabilities, SCAN, IJTAG (IEEE 1687), and boundary scan (IEEE 1149.1/6) • Proven track record with FinFET nodes (7nm, 5nm, or below) • Experience managing DFT in multi-voltage/power-gated designs