Principal ASIC Integration Engineer

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🔥 0 minutes ago

🇪🇺 Europe – Remote

⏳ Contract/Temporary

🔴 Lead

💻 Solutions Engineer

👻 Ghost score 10%

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Avenga

WebsiteLinkedInAll Job Openings

5001 - 10000 employees

💼 Consulting

🏭 Manufacturing

🏥 Healthcare

💰 Private equity on 2017-02

Consulting • Manufacturing • Healthcare

Avenga is an international technology and software engineering company that combines consulting, product development, and digital transformation services to help enterprises solve complex business and societal challenges. With over 6,000 professionals across multiple countries and decades of experience, Avenga delivers custom software, cloud, and integration solutions while supporting clients across industries and providing talent acquisition and career development services internally.

📋 Description

• Collaborate with electrical engineers to define requirements, evaluate architectural options, and develop ASIC specifications • Lead system-level trade-off analyses across performance, power, die size, unit cost, manufacturability, yield, and production readiness • Lead technical evaluation, selection, and integration of third-party analog, compute, memory, and other semiconductor IP • Represent the electrical engineering team in technical discussions with foundries, OSAT partners, and IP vendors • Track semiconductor technology roadmaps and address manufacturing constraints and bottlenecks with external partners • Influence process-node and PDK selection based on performance, power, cost, yield, and foundry maturity • Drive Design-for-Cost, Design-for-Manufacturing, Design-for-Assembly, and Design-for-Yield considerations throughout architecture and design • Guide floorplanning, die-size optimization, pin count and placement, and packaging decisions • Provide technical input to semiconductor cost models covering wafer economics, OSAT location, packaging, test time, yield, and unit-cost drivers • Partner with test and validation engineers to define strategies maximizing fault coverage while minimizing test time and production costs • Incorporate supply-chain resilience and multi-sourcing flexibility into architectural and manufacturing decisions • Analyze production-line yields and silicon test data to identify continuous-improvement opportunities • Collaborate with technical and commercial stakeholders throughout the complete ASIC lifecycle, from architecture and technology selection to tape-out, manufacturing, testing, and yield optimization

🎯 Requirements

• At least 8 years of experience in ASIC microarchitecture, ASIC design, or SoC design within an electrical engineering environment • Multiple successful ASIC or SoC tape-outs • Experience taking designs through the full development lifecycle • Strong understanding of ASIC and SoC architecture and microarchitecture, including system-level architectural trade-offs • Hands-on experience evaluating, selecting, and integrating third-party semiconductor IP, including analog, compute, and memory IP • Understanding of semiconductor foundry processes, process nodes, and PDKs • Knowledge of semiconductor packaging, assembly, testing methodologies, fault coverage, and production-test optimization • Understanding of yield fundamentals, silicon test data, production-line yield analysis, and yield optimization • Familiarity with Design-for-Cost, Design-for-Manufacturing, Design-for-Assembly, and Design-for-Yield principles • Understanding of wafer economics, OSAT operations, packaging and test costs, and semiconductor unit-cost drivers • Ability to evaluate technical decisions in the context of system BOM cost, manufacturing feasibility, production timelines, and supply-chain risk • Comfortable collaborating with foundries, OSAT partners, IP vendors, and multidisciplinary internal teams • Availability for regular international business travel, particularly to Denmark

🏖️ Benefits

• Equal opportunities in recruitment, career development, and leadership • International engineering project engagement expected to last at least one year, with possibility of extension for an additional year