Digital Flow Enablement Solutions Architect

Job not on LinkedIn

🕒 March 27

🏄 California, Massachusetts – Remote

🏄 California – Remote 🍂 Massachusetts – Remote

💵 $157.5k - $292.5k / year

⏰ Full Time

🟠 Senior

🔴 Lead

💻 Solutions Engineer

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Cadence Design Systems

WebsiteLinkedInAll Job Openings

10,000+ employees

Cadence is a pivotal leader in electronics and system design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.

📋 Description

• Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development. • Interfacing with customers regarding digital flow enablement and methodologies, including: timing characterization, including sensitivity modeling, Physical view generation (LEF, GDS, abstracts, etc) Logical view generation (LIB, CDL, Spectre, etc) Technology LEF creation for digital tools MSOA flows • Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness • Tempus timing flow development and validation • Working closely with R&D on tools and methodology improvements • Other digital P&R tasks as needed by the group • Processes nodes range from 1.4nm to 350nm, with majority of work at GAA advanced nodes

🎯 Requirements

• Bachelor’s degree with at least 12-16 years of design/EDA experience or Master’s degree with at least 10 years of experience. • Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects • Excellent digital simulation and debug skills • Experience with techLEF development at advanced nodes a must • Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM • Strong knowledge of Digital Design flows and Static Timing Analysis • Prior experience with ASIC digital implementation flows and EDA tools is required • Experience with advanced nodes (5nm and below) required. • Good programming knowledge in Unix, Shell scripting, perl and importantly TCL • Strong customer-facing communication and problem solving skills • Strong personal drive for continuous learning and expanding professional skill sets • Excellent verbal and written communication skills • Familiar with EDA tool: Characterization: Liberate, Liberate MX, Liberate AMS Simulators: Spectre, AMS, Xcelium Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc

🏖️ Benefits

• paid vacation and paid holidays • 401(k) plan with employer match • employee stock purchase plan • a variety of medical, dental and vision plan options • and more.