Analog Layout Engineer

🔥 0 minutes ago

🇺🇦 Ukraine – Remote

⏰ Full Time

🟡 Mid-level

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 12%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Capgemini

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1967

💼 Consulting

🏥 Healthcare

📦 Logistics

Consulting • Healthcare • Logistics

Capgemini is a global leader in partnering with businesses to transform and manage their operations by harnessing the power of technology. With expertise across a wide array of industries such as aerospace, automotive, banking, and healthcare, Capgemini provides a constantly evolving portfolio of services to meet the ever-changing needs of their clients. Their offerings include cloud, cybersecurity, data and artificial intelligence, and enterprise management, among others. Capgemini also emphasizes innovation and sustainability, helping companies achieve digital transformation while promoting environmental and social responsibility. Additionally, Capgemini provides career opportunities across various levels and professions, encouraging innovation and diversity in its workforce.

📋 Description

• Develop analog layouts for amplifiers, references, bias blocks, and data converters in FinFET nodes • Apply best practices for DRC/LVS closure, including advanced debugging techniques • Perform EM/IR analysis and implement layout changes to meet reliability targets • Address parasitic effects through routing, shielding, and post-extraction corrections • Implement matching techniques including common-centroid, interdigitation, and dummy devices • Collaborate with circuit designers to optimize layout for performance and yield • Ensure compliance with color-aware routing and multi-patterning constraints (SADP/SAQP)

🎯 Requirements

• Proven experience in FinFET layout design for analog IP • Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies • Proficiency in industry-standard EDA tools (Cadence Virtuoso, Calibre, PVS) • Familiarity with parasitic extraction flows and correlation techniques • Understanding of reliability mechanisms (BTI, HCI) and guard-banding in layout • Experience with advanced-node design rules and color-aware layout • Knowledge of EM/IR verification methodologies and sign-off flows • Ability to automate layout tasks using SKILL or Python scripts

🏖️ Benefits

• Health insurance from the first days, regardless of the probationary period • Christmas holidays from 25 December to 31 December • Cooperation with Superhumans center and Veteran HUB • Psychological counseling provided by the Veteran Hub • Internal policy making the company friendly to military and veterans