Middle RTL Engineer

Job not on LinkedIn

🕒 July 19

🇺🇦 Ukraine – Remote

⏰ Full Time

🟡 Mid-level

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 22%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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Capgemini

WebsiteLinkedInAll Job Openings

10,000+ employees

Founded 1967

💼 Consulting

🏥 Healthcare

📦 Logistics

Consulting • Healthcare • Logistics

Capgemini is a global leader in partnering with businesses to transform and manage their operations by harnessing the power of technology. With expertise across a wide array of industries such as aerospace, automotive, banking, and healthcare, Capgemini provides a constantly evolving portfolio of services to meet the ever-changing needs of their clients. Their offerings include cloud, cybersecurity, data and artificial intelligence, and enterprise management, among others. Capgemini also emphasizes innovation and sustainability, helping companies achieve digital transformation while promoting environmental and social responsibility. Additionally, Capgemini provides career opportunities across various levels and professions, encouraging innovation and diversity in its workforce.

📋 Description

• Implement design microarchitecture at RTL level for high-performance blocks based on functional specifications from senior engineers and architects • Perform RTL debugging, ensuring design correctness and efficiency • Run and analyze lint checks and CDC checks • Collaborate with verification, physical design, and architecture teams • Contribute to front-end synthesis and optimization • Work on SoC-level integration and design • Apply power optimization techniques for energy-efficient designs

🎯 Requirements

• 3+ years of hands-on experience in digital design • Willingness to constantly learn from senior colleagues • Strong knowledge of Verilog and/or VHDL for synthesis • Familiarity with SystemVerilog is a plus • Experience with tools like Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler is a plus • Proven experience in RTL design, uArch development, and functional specs • Basic understanding of linting tools, CDC methodologies, and debugging flows • Familiarity with synthesis tools and SoC design is a strong plus • Bachelor's degree in EE, ECE, CE, CS, or a related field required • MS or PhD highly desired • Good communication and collaboration skills

🏖️ Benefits

• Health insurance from the first days, regardless of the probationary period • Christmas holidays from December 25 to December 31 • Cooperation with Superhumans center and Veteran HUB • Psychological counseling provided by the Veteran Hub • Internal policy making the company friendly to military and veterans