Ciena
5001 - 10000 employees
Founded 1985
📡 Telecommunications
🔧 Hardware
💰 Series C on 1995-12
Telecommunications • Hardware • Networking
Ciena is a global leader in optical and routing systems, services, and automation software. We build the world’s most adaptive networks to address ever-increasing digital demands for richer, more connected experiences for all users. For three-plus decades, we’ve brought our innate sense of humanity to our relentless pursuit of innovation.
Principal SerDes System – DSP Design Engineer
🕒 January 28
DAC
Python
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Ciena
5001 - 10000 employees
Founded 1985
📡 Telecommunications
🔧 Hardware
💰 Series C on 1995-12
Telecommunications • Hardware • Networking
Ciena is a global leader in optical and routing systems, services, and automation software. We build the world’s most adaptive networks to address ever-increasing digital demands for richer, more connected experiences for all users. For three-plus decades, we’ve brought our innate sense of humanity to our relentless pursuit of innovation.
📋 Description
• Lead the architecture, design, and validation of high-speed serial transceivers across electrical and optical domains • Leverage expertise in systems engineering, control theory, DSP algorithms, and modeling to develop cutting-edge serial electrical/optical-IMDD transceiver solutions • Perform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques • Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms • Integrate control theory and advanced DSP designs into feasible hardware implementations • Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems • Conduct design trade-offs to meet stringent performance, power, and area targets • Analyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin • Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps
🎯 Requirements
• Advanced expertise in electrical SerDes DSP design and implementation • Proven experience in SerDes system-level evaluation, modeling, and simulation • Strong proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems • Familiarity with optical IMDD (Intensity Modulation Direct Detection) systems • Deep understanding of adaptive equalization techniques for high-speed links • Proficiency with maximum likelihood sequence detection (MLSD) approaches • Expertise in timing recovery schemes in high-speed serial links • Practical knowledge of FEC performance modeling and system-level performance optimization • Experience with MATLAB, Python, or C/C++ for algorithm design and simulation • Strong problem-solving skills and ability to work across hardware/software boundaries • Ph.D. in Electrical Engineering with background in digital communications and signal processing • 8+ years of experience in high-speed serial link or communication system design
🏖️ Benefits
• medical, dental, and vision plans • participation in 401(K) (USA) & DCPP (Canada) with company matching • Employee Stock Purchase Program (ESPP) • Employee Assistance Program (EAP) • company-paid holidays • paid sick leave • vacation time • comply with all applicable laws regarding Paid Family Leave and other leaves of absence
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