Design Verification Engineer

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July 17

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Corinex

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Energy • SaaS • Telecommunications

Corinex is a world leader in Broadband over Power Lines (BPL) technology, offering solutions that provide unparalleled grid visibility and flexibility for utilities. The company focuses on accelerating the integration of intelligent energy systems, helping energy companies, electric utilities, EV manufacturers, and EV charging providers address pressing climate and energy challenges. Corinex's comprehensive offerings include grid digitalization solutions like smart grid applications, advanced metering infrastructure, and vehicle-to-grid (V2G) applications. With a focus on local grid flexibility and data processing, Corinex empowers decentralized grids with millions of near real-time connections, facilitating the management of distributed energy resources and enhancing system observability, monitoring, control, and protection.

51 - 200 employees

⚡ Energy

☁️ SaaS

📡 Telecommunications

📋 Description

• Verify highly complex SoCs and support verification development. • Architect and develop the functional verification environment, including reference models, testbench development, and testcase execution. • Write test plans using random techniques and coverage analysis. • Work closely with mixed signal teams for integration of high-speed analog behavioural models. • Debug failures and work with designers to resolve issues. • Cooperate with Synthesis, DFT, STA, and PnR to implement subsystems that meet challenging PPA requirements. • Support Emulation, functional ATE, and silicon validation teams.

🎯 Requirements

• Proficiency in verification languages, including UVM and System Verilog. • Experience with block, cluster/subsystem, and top-level verification. • Hands-on experience in test bench development, including agents, drivers, checkers, and interfaces for complex designs. • Strong understanding of verification methodologies such as test plan creation, direct and random test cases, formal test cases, and coverage analysis. • Full-cycle verification experience, from architecture to tape-out, with expertise in test plan development, debugging, coverage closure, and gate-level simulation. • Proven experience in top-level verification of complex SoC designs. • Expertise in high-speed protocols, particularly Ethernet. • Proficiency in scripting languages such as Python and Bash. • Knowledge in one or more domains: networking, embedded systems architecture, computer architecture, and machine learning accelerators. • General understanding of IC design, design-for-test (DFT), and design-for-manufacturing (DFM). • Familiarity with digital design methodologies, ASIC design flows, and industry-leading verification EDA tools. • Ability to work effectively in a collaborative team environment. • Strong communication skills in English.