Team Lead - Digital Design Verification

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May 10

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Corinex

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Energy • SaaS • Telecommunications

Corinex is a world leader in Broadband over Power Lines (BPL) technology, offering solutions that provide unparalleled grid visibility and flexibility for utilities. The company focuses on accelerating the integration of intelligent energy systems, helping energy companies, electric utilities, EV manufacturers, and EV charging providers address pressing climate and energy challenges. Corinex's comprehensive offerings include grid digitalization solutions like smart grid applications, advanced metering infrastructure, and vehicle-to-grid (V2G) applications. With a focus on local grid flexibility and data processing, Corinex empowers decentralized grids with millions of near real-time connections, facilitating the management of distributed energy resources and enhancing system observability, monitoring, control, and protection.

51 - 200 employees

⚡ Energy

☁️ SaaS

📡 Telecommunications

📋 Description

•We are looking for an Digital Design Verification Team Lead to join our Valencia R&D team. •The candidate will be integrated into a dynamic, cross-functional, experienced team to do functional verification tests in Verilog and C, for million-plus gate ASICs targeted for Smart Grid applications. •Work directly with ASIC and board designers to ensure a smooth transition from project definition through prototyping to mass production. •Define and implement test procedures to ensure the maximum level of product quality. •Improve manufacturing yields and costs through creative thinking and innovative ideas. •Build up and manage Digital Verification Team. •Verify highly complex SoCs and support verification development. •Architect and develop the functional verification environment, including reference models, testbench development, and testcase execution. •Write test plans using random techniques and coverage analysis. •Work closely with mixed signal teams for integration of high-speed analog behavioral models. •Debug failures and work with designers to resolve issues. •Cooperate with Synthesis, DFT, STA, PnR to implement subsystems that meet challenging PPA requirements. •Support Emulation, functional ATE, and silicon validation teams.

🎯 Requirements

•Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field. •Minimum 5 years of experience in Digital Design Verification activities. •Proficiency in verification languages, including UVM and SystemVerilog. •Experience with verification at block level, cluster/subsystem level, and top level. •Hands-on experience in test bench development, including agents, drivers, checkers, and interfaces for complex designs. •Strong understanding of verification methodologies such as test plan creation, direct and random test cases, formal test cases, and coverage analysis. •Full-cycle verification experience, from architecture to tape-out, with expertise in test plan development, debugging, coverage closure, and gate-level simulation. •Proven experience in top-level verification of complex SoC designs. •Expertise in high-speed protocols, particularly Ethernet. •Proficiency in scripting languages such as Python and Bash. •Knowledge in one or more of the following domains: networking, embedded systems architecture, computer architecture, machine learning accelerators. •General understanding of IC design, design-for-test (DFT), and design-for-manufacturing (DFM). •Familiarity with digital design methodologies, ASIC design flows, and industry-leading verification EDA tools. •Ability to work effectively in a collaborative team environment. •Strong communication skills in English.