
501 - 1000 employees
Founded 1905
📚 Education
🔬 Science
Education • Engineering • Science
University of Washington, Department of Electrical & Computer Engineering is an academic department that focuses on advancing education and research in electrical and computer engineering. It provides a range of undergraduate and graduate programs, emphasizes innovation in engineering, and conducts cutting-edge research in various fields such as microelectronics, robotics, and quantum technology. The department fosters a diverse and inclusive community and offers numerous opportunities for students to engage in hands-on learning, research, and collaboration with industry leaders.
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501 - 1000 employees
Founded 1905
📚 Education
🔬 Science
Education • Engineering • Science
University of Washington, Department of Electrical & Computer Engineering is an academic department that focuses on advancing education and research in electrical and computer engineering. It provides a range of undergraduate and graduate programs, emphasizes innovation in engineering, and conducts cutting-edge research in various fields such as microelectronics, robotics, and quantum technology. The department fosters a diverse and inclusive community and offers numerous opportunities for students to engage in hands-on learning, research, and collaboration with industry leaders.
• Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan • Work closely with the analog and digital design teams on floor planning and signal distribution • Coordinate with program managers to track layout and floorplan activities • Conduct layout reviews and complete full-chip closure activities • Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks • Participate in the IC layout methodology roadmap
• Bachelor’s or master’s degree in computer or electrical engineering or a related technical field, with 12+ years of experience • Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from conception to tapeout • Expert in full-chip/SOC-level floorplanning and integration • Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm • Strong technical project management skills • Ability to lead and mentor other layout engineers
• Health insurance • 401(k) plan and company match • Merit increases • Annual bonus • Stock options • Open paid time-off policy
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