Senior Logic Design Engineer

Job not on LinkedIn

🔥 53 minutes ago

🌐 Ukraine, Romania, +2 more countries – Remote

🇺🇦 Ukraine – Remote 🇷🇴 Romania – Remote 🇧🇬 Bulgaria – Remote 🇵🇱 Poland – Remote

⏰ Full Time

🟠 Senior

🧑‍🔧 Mechanical Engineer

👻 Ghost score 10%

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Helpware

WebsiteLinkedInAll Job Openings

1001 - 5000 employees

Founded 2015

📦 Logistics

📣 Marketing

💼 Consulting

💰 Seed Round on 2016-01

Logistics • Marketing • Consulting

Helpware is a digitally enabled People as a Services Outsourcer dedicated to enhancing customer experiences for high-growth, market-disrupting, and technology companies. They specialize in providing a wide array of services such as digital customer experience, content control and verification, AI-driven customer service, back-office support, and data labeling. Helpware also assists in areas like digital marketing support, cybersecurity, and software development. Operating globally, they offer culturally aligned and scalable team solutions across multiple countries. Helpware aims to drive brand loyalty and efficiency for its clients by providing human task services integrated with technology solutions.

📋 Description

• Design and implement complex, configurable, low-latency RTL modules using SystemVerilog • Develop digital logic for high-performance FPGA and ASIC applications, including signal processing, waveform generation, and real-time control • Participate in the complete RTL development lifecycle, from architecture and microarchitecture definition to implementation and verification • Optimize RTL designs for timing, latency, resource utilization, and power efficiency • Perform logic synthesis, timing analysis, and optimization to meet design constraints • Collaborate with verification engineers to ensure functional correctness and comprehensive test coverage • Analyze system-level and software requirements and implement appropriate hardware-software interfaces • Integrate proprietary digital IP into complex FPGA/ASIC architectures • Participate in design reviews, debugging, and continuous improvement of engineering processes

🎯 Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience • 4+ years of professional experience in FPGA or ASIC digital logic design • Strong practical experience in RTL development using SystemVerilog (mandatory) • Solid understanding of digital logic design, computer architecture, and RTL microarchitecture • Experience with logic synthesis, static timing analysis (STA), and timing optimization • Practical experience with FPGA or ASIC design and implementation workflows • Understanding of clock-domain crossing (CDC), synchronous digital design, and hardware interfaces • Experience with simulation-based RTL verification and debugging • Strong analytical, problem-solving, and communication skills • English proficiency sufficient for effective collaboration within an international engineering team