
11 - 50 employees
Founded 2012
🤖 Artificial Intelligence
🔧 Hardware
💰 $70M Series C on 2021-05
Artificial Intelligence • Hardware • Robotics
Mythic is the leading high-performance analog computing company that focuses on delivering cost-efficient and energy-efficient edge AI computing power across various sectors including robotics, defense, and consumer devices. The company's innovative compute-in-memory technology solves the limitations of traditional digital computing by storing AI parameters directly in the processor, significantly enhancing AI inference applications. Mythic aims to empower industries with advancements in performance scalability and efficiency, providing a robust platform for the next generation of AI applications.
🕒 March 19
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11 - 50 employees
Founded 2012
🤖 Artificial Intelligence
🔧 Hardware
💰 $70M Series C on 2021-05
Artificial Intelligence • Hardware • Robotics
Mythic is the leading high-performance analog computing company that focuses on delivering cost-efficient and energy-efficient edge AI computing power across various sectors including robotics, defense, and consumer devices. The company's innovative compute-in-memory technology solves the limitations of traditional digital computing by storing AI parameters directly in the processor, significantly enhancing AI inference applications. Mythic aims to empower industries with advancements in performance scalability and efficiency, providing a robust platform for the next generation of AI applications.
• Join us in building the next generation of AI compilers. You’ll play a key role in developing the compiler for our novel AI accelerator, working side-by-side with hardware engineers and ML researchers. • Your work will shape how deep learning workloads run on cutting-edge dataflow hardware—defining the instruction set, execution model, and developer experience. • The result: a compiler that delivers breakthrough performance while remaining seamless and intuitive for ML developers. • Contribute across the full compiler stack, including operator lowering, graph/IR transformations, optimization passes, and backend code generation • Optimize for dataflow architectures, developing pipelined schedules, memory orchestration, and resource-constrained execution strategies • Collaborate with hardware architects to influence architectural features, ensuring the compiler and hardware evolve together • Develop compilation strategies that unify our analog compute with digital subsystems • Build and maintain a compiler that produces high-performance binaries with strong debugging support, clear error messages, and predictable performance models
• 3+ years of experience building compilers or high-performance systems software, especially those involving complex resource management or optimization. • Expert in modern C++ (C++14/17/20) and strong Python. • Experience with compiler IRs (SSA-based or graph-based), transformations, and code generation • Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with contributions to MLIR or LLVM projects a plus • Experience with optimization methods (LP/MIP, CP, SAT/SMT) using solvers like Gurobi or OR-Tools for scheduling and resource allocation • Experience compiling for specialized accelerators (GPU, NPU, FPGA, or custom ASIC) on DNN workloads; GPU/DSP experience is valuable if combined with compiler backend work beyond kernel tuning • Familiarity with heterogeneous compilation, especially mixing custom accelerators with CPUs/GPUs/NPUs, and exposure to analog or in-memory compute is a plus • Experience collaborating in compiler–hardware co-design (architecture + ISA) for better compiler usability and hardware efficiency
• Competitive compensation, equity, and benefits package • A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design. We foster an environment of shared learning and technical excellence • The opportunity to shape how deep learning and LLM workloads are compiled on novel hardware. • A role that spans software and hardware co-design, shaping both the compiler and the accelerator architecture
Apply Now🕒 March 18
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