Senior Formal Verification Engineer

Job not on LinkedIn

🕒 July 10

🇪🇸 Spain – Remote

⏰ Full Time

🟠 Senior

👷🏻‍♀️ Engineer

👻 Ghost score 24%

What it means: how likely this posting is sitting open without active hiring.How to read it: 60% or higher means we think this is a ghost. Lower scores are less of a worry.How we score it: age, reposts, open roles vs team size, how fast jobs close, and whether pay is listed.Fine print: an estimate from public data, not a judgment of the company. Real jobs can score high, so treat it as a hint, not a fact.

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TechBiz Global

WebsiteLinkedInAll Job Openings

51 - 200 employees

📣 Marketing

📦 Logistics

🎯 Recruiter

Marketing • Logistics • Recruitment

TechBiz Global is a leading recruitment and software development company that specializes in connecting businesses with top-tier talent across 28+ countries. They serve clients from startups to major enterprises, providing expertise in hiring key roles in industries such as FinTech. In addition to talent acquisition, TechBiz Global offers comprehensive software development services to turn clients' visions into reality, powering digital transformations with expert engineers. The company also provides strategic CTO consulting services and flexible outstaffing and outsourcing solutions, helping businesses manage growth and optimize technology processes. Recognized as a top IT recruitment and consulting firm, TechBiz Global is dedicated to delivering personalized and innovative solutions to its clients, ensuring they have the tools necessary for success.

📋 Description

• Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. • Design scalable formal testbenches, write mathematical properties, and ensure the algorithmic and architectural integrity of the vector pipeline. • Work with VU microarchitects to identify deep corner-case bugs and achieve formal sign-off on complex arithmetic and execution blocks. • Design, deploy, and maintain robust formal verification environments for Vector Unit sub-blocks. • Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify floating-point and integer vector arithmetic units. • Independently diagnose and resolve proof-convergence failures using advanced reduction techniques. • Develop formal environments to mathematically prove compliance with RISC-V Vector Extension specifications. • Collaborate closely with VU simulation engineers for maximum bug-hunting efficiency.

🎯 Requirements

• B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic. • 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines. • A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team. • Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. • Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. • Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin).

🏖️ Benefits

• Flexible working hours • Professional development opportunities