Lead / Principal Engineer, Ethernet Scale - Up

🕒 September 16

🇮🇳 India – Remote

⏰ Full Time

🟠 Senior

🧑‍💻 Full-stack Engineer

👻 Ghost score 30%

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TYLsemi

WebsiteLinkedInAll Job Openings

11 - 50 employees

Founded 2026

🔧 Hardware

🤖 Artificial Intelligence

🤝 B2B

Hardware • Artificial Intelligence • B2B

TYLsemi is a chiplet-first silicon company focused on AI infrastructure solutions. It provides production-ready, validated chiplets and a unified platform to take designs from architecture to deployed silicon, enabling faster, lower-risk development of AI systems. TYLsemi's offerings (branded TYL. IO, TYL. Power, TYL. Forge) target critical AI infrastructure functions—XPUs, switches, connectivity, power, and system scaling—and it also offers chiplet-enabled custom silicon, packaging, and manufacturing integration. The company promotes up to ~50% faster development and reduced costs, and recently raised $43M in an oversubscribed early-stage funding round.

📋 Description

• Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics • Lead development of high-performance Ethernet subsystem microarchitectures, including RDMA, packet processing, network offload, traffic management, congestion control, and reliability mechanisms • Drive execution from architecture through RTL, verification, physical design, silicon bring-up, and production • Optimize performance, latency, scalability, power, and reliability for demanding AI and HPC workloads • Collaborate across hardware, firmware, software, and system teams to deliver AI networking solutions • Serve as a company-wide technical leader influencing product strategy, roadmap, and architectural direction • Define and validate Ethernet Scale-Up Networking architecture for next-generation HPC and rack-scale AI systems • Deliver production-quality Ethernet subsystem microarchitecture on schedule • Align and unblock cross-functional teams across hardware, firmware, software, and systems

🎯 Requirements

• 15+ years of ASIC/SoC architecture and design experience • Proven track record delivering networking, NIC, switch, DPU, accelerator interconnect, or high-speed connectivity silicon • Deep expertise in SystemVerilog/RTL design and high-performance datapath architecture • Strong knowledge of Ethernet, RDMA, traffic management, congestion control, and scalable fabric architectures • Experience across the full ASIC lifecycle, from architecture to production silicon • Ultra Ethernet, UALink, RoCEv2, InfiniBand, PCIe Gen6/Gen7, UCIe, CXL, AI/HPC interconnects, and collective communication acceleration • Experience with 400G/800G/1.6T Ethernet systems • Experience with high-speed SerDes and advanced networking architectures

🏖️ Benefits

• Remote-friendly work arrangement • Opportunity to work with a global team • Opportunity to work on consequential AI/HPC silicon infrastructure • Ownership of technical roadmap and architectural direction • High-impact role with company-wide technical influence

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